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Searched refs:REG_BIT (Results 1 – 25 of 54) sorted by relevance

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/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_gt_regs.h50 #define MCR_MULTICAST REG_BIT(31)
66 #define LE_SCF_MASK REG_BIT(14)
72 #define LE_RSC_MASK REG_BIT(7)
74 #define LE_AOM_MASK REG_BIT(6)
87 #define CG_DIS_CNTLBUS REG_BIT(6)
95 #define AUX_INV REG_BIT(0)
104 #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10)
107 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
108 #define DIS_CLIP_NEGATIVE_BOUNDING_BOX REG_BIT(6)
111 #define TBIMR_FAST_CLIP REG_BIT(5)
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Dxe_guc_regs.h21 #define DRB_VALID REG_BIT(0)
25 #define GTCR_INVALIDATE REG_BIT(0)
41 #define GS_MIA_IN_RESET REG_BIT(0)
47 #define GUC_WOPCM_SIZE_LOCKED REG_BIT(0)
51 #define GUC_SHIM_WC_ENABLE REG_BIT(21)
52 #define GUC_ENABLE_MIA_CLOCK_GATING REG_BIT(15)
53 #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA REG_BIT(10)
54 #define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA REG_BIT(9)
55 #define GUC_MSGCH_ENABLE REG_BIT(4)
56 #define GUC_ENABLE_MIA_CACHING REG_BIT(2)
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Dxe_oa_regs.h10 #define GT_NOA_ENABLE REG_BIT(9)
25 #define OAR_OACONTROL_COUNTER_ENABLE REG_BIT(0)
29 #define OA_COUNTER_RESUME REG_BIT(0)
34 #define OAG_OAGLBCTXCTRL_TIMER_ENABLE REG_BIT(1)
35 #define OAG_OAGLBCTXCTRL_COUNTER_RESUME REG_BIT(0)
52 #define OAG_OABUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */
58 #define OAG_OACONTROL_OA_COUNTER_ENABLE REG_BIT(0)
64 #define OAG_OA_DEBUG_DISABLE_MMIO_TRG REG_BIT(14)
65 #define OAG_OA_DEBUG_START_TRIGGER_SCOPE_CONTROL REG_BIT(13)
66 #define OAG_OA_DEBUG_DISABLE_START_TRG_2_COUNT_QUAL REG_BIT(8)
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Dxe_engine_regs.h61 #define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
62 #define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
63 #define IDLE_MSG_DISABLE REG_BIT(0)
91 #define ENABLE_SEMAPHORE_POLL_BIT REG_BIT(13)
105 #define GHWSP_CSB_REPORT_DIS REG_BIT(15)
106 #define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14)
107 #define CS_PRIORITY_MEM_READ REG_BIT(7)
110 #define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
113 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
114 #define REPLAY_MODE_GRANULARITY REG_BIT(0)
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Dxe_regs.h16 #define GU_MISC_GSE REG_BIT(27)
19 #define DRIVERINT_FLR_DIS REG_BIT(31)
22 #define LMEM_INIT REG_BIT(7)
23 #define DRIVERFLR REG_BIT(31)
26 #define SGSI_SIDECLK_DIS REG_BIT(17)
29 #define DRIVERFLR_STATUS REG_BIT(31)
32 #define GUEST_GTT_UPDATE_EN REG_BIT(8)
61 #define DG1_MSTR_IRQ REG_BIT(31)
62 #define DG1_MSTR_TILE(t) REG_BIT(t)
65 #define MASTER_IRQ REG_BIT(31)
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Dxe_gsc_regs.h20 #define HECI_H_CSR_IE REG_BIT(0)
21 #define HECI_H_CSR_IS REG_BIT(1)
22 #define HECI_H_CSR_IG REG_BIT(2)
23 #define HECI_H_CSR_RDY REG_BIT(3)
24 #define HECI_H_CSR_RST REG_BIT(4)
34 #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
39 #define HECI1_FWSTS5_HUC_AUTH_DONE REG_BIT(19)
43 #define HECI_H_GS1_ER_PREP REG_BIT(0)
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_dsb_regs.h18 #define DSB_ENABLE REG_BIT(31)
19 #define DSB_BUF_REITERATE REG_BIT(29)
20 #define DSB_WAIT_FOR_VBLANK REG_BIT(28)
21 #define DSB_WAIT_FOR_LINE_IN REG_BIT(27)
22 #define DSB_HALT REG_BIT(16)
23 #define DSB_NON_POSTED REG_BIT(8)
24 #define DSB_STATUS_BUSY REG_BIT(0)
26 #define DSB_MMIO_DEAD_CLOCKS_ENABLE REG_BIT(31)
32 #define DSB_POLL_ENABLE REG_BIT(31)
40 #define DSB_HP_IDLE_STATUS REG_BIT(31)
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Dintel_psr_regs.h13 #define EXITLINE_ENABLE REG_BIT(31)
27 #define EDP_PSR_ENABLE REG_BIT(31)
28 #define BDW_PSR_SINGLE_FRAME REG_BIT(30)
29 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */
30 #define EDP_PSR_LINK_STANDBY REG_BIT(27)
40 #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12)
41 #define EDP_PSR_TP_MASK REG_BIT(11)
44 #define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */
74 #define TGL_PSR_ERROR REG_BIT(2)
75 #define TGL_PSR_POST_EXIT REG_BIT(1)
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Dintel_hdcp_regs.h15 #define HDCP_AKSV_SEND_TRIGGER REG_BIT(31)
16 #define HDCP_CLEAR_KEYS_TRIGGER REG_BIT(30)
17 #define HDCP_KEY_LOAD_TRIGGER REG_BIT(8)
19 #define HDCP_FUSE_IN_PROGRESS REG_BIT(7)
20 #define HDCP_FUSE_ERROR REG_BIT(6)
21 #define HDCP_FUSE_DONE REG_BIT(5)
22 #define HDCP_KEY_LOAD_STATUS REG_BIT(1)
23 #define HDCP_KEY_LOAD_DONE REG_BIT(0)
29 #define HDCP_TRANSA_REP_PRESENT REG_BIT(31)
30 #define HDCP_TRANSB_REP_PRESENT REG_BIT(30)
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Dintel_fbc_regs.h12 #define FBC_CTL_EN REG_BIT(31)
13 #define FBC_CTL_PERIODIC REG_BIT(30)
16 #define FBC_CTL_STOP_ON_MOD REG_BIT(15)
17 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
18 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
24 #define FBC_CMD_COMPRESS REG_BIT(0)
26 #define FBC_STAT_COMPRESSING REG_BIT(31)
27 #define FBC_STAT_COMPRESSED REG_BIT(30)
28 #define FBC_STAT_MODIFIED REG_BIT(29)
31 #define FBC_CTL_FENCE_DBL REG_BIT(4)
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Dintel_dvo_regs.h15 #define DVO_ENABLE REG_BIT(31)
16 #define DVO_PIPE_SEL_MASK REG_BIT(30)
22 #define DVO_INTERRUPT_SELECT REG_BIT(27)
23 #define DVO_DEDICATED_INT_ENABLE REG_BIT(26)
25 #define DVO_USE_VGA_SYNC REG_BIT(15)
26 #define DVO_DATA_ORDER_MASK REG_BIT(14)
29 #define DVO_VSYNC_DISABLE REG_BIT(11)
30 #define DVO_HSYNC_DISABLE REG_BIT(10)
31 #define DVO_VSYNC_TRISTATE REG_BIT(9)
32 #define DVO_HSYNC_TRISTATE REG_BIT(8)
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Dintel_dp_aux_regs.h46 #define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
47 #define DP_AUX_CH_CTL_DONE REG_BIT(30)
48 #define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
49 #define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
55 #define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25)
60 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) /* mtl+ */
61 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) /* mtl+ */
62 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15)
63 #define DP_AUX_CH_CTL_MANCHESTER_TEST REG_BIT(14) /* pre-hsw */
64 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL REG_BIT(14) /* skl+ */
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Dintel_cx0_phy_regs.h43 #define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
50 #define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
63 #define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
69 #define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
94 #define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
95 #define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
96 #define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
101 #define XELPDP_PORT_REVERSAL REG_BIT(16)
102 #define XELPDP_PORT_BUF_IO_SELECT_TBT REG_BIT(11)
103 #define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7)
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Dvlv_dpio_phy_regs.h41 #define DPIO_ENABLE_CALIBRATION REG_BIT(11)
48 #define DPIO_REFSEL_OVERRIDE REG_BIT(27)
75 #define DPIO_PCS_TX_LANE2_RESET REG_BIT(16)
76 #define DPIO_PCS_TX_LANE1_RESET REG_BIT(7)
77 #define DPIO_LEFT_TXFIFO_RST_MASTER2 REG_BIT(4)
78 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 REG_BIT(3)
83 #define CHV_PCS_REQ_SOFTRESET_EN REG_BIT(23)
84 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN REG_BIT(22)
85 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21)
90 #define DPIO_PCS_CLK_SOFT_RESET REG_BIT(5)
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Dintel_vrr_regs.h17 #define VRR_CTL_VRR_ENABLE REG_BIT(31)
18 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
19 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
22 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
47 #define VRR_VMAXSHIFT_DEC REG_BIT(16)
55 #define VRR_STATUS_VMAX_REACHED REG_BIT(31)
56 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
57 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
58 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
59 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
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Dbxt_dpio_phy_regs.h37 #define PORT_PLL_ENABLE REG_BIT(31)
38 #define PORT_PLL_LOCK REG_BIT(30)
39 #define PORT_PLL_REF_SEL REG_BIT(27)
40 #define PORT_PLL_POWER_ENABLE REG_BIT(26)
41 #define PORT_PLL_POWER_STATE REG_BIT(25)
58 #define PORT_PLL_RECALIBRATE REG_BIT(14)
59 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
77 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
92 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
104 #define PHY_POWER_GOOD REG_BIT(16)
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Dintel_sprite_regs.h13 #define DVS_ENABLE REG_BIT(31)
14 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
15 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
21 #define DVS_PIPE_CSC_ENABLE REG_BIT(24)
22 #define DVS_SOURCE_KEY REG_BIT(22)
23 #define DVS_RGB_ORDER_XBGR REG_BIT(20)
24 #define DVS_YUV_FORMAT_BT709 REG_BIT(18)
30 #define DVS_ROTATE_180 REG_BIT(15)
31 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
32 #define DVS_TILED REG_BIT(10)
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Di9xx_plane_regs.h16 #define DISP_ENABLE REG_BIT(31)
17 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
32 #define DISP_STEREO_ENABLE REG_BIT(25)
33 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
36 #define DISP_SRC_KEY_ENABLE REG_BIT(22)
37 #define DISP_LINE_DOUBLE REG_BIT(20)
38 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
39 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
40 #define DISP_ROTATE_180 REG_BIT(15) /* i965+ */
41 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) /* pre-g4x plane B */
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Dintel_snps_phy_regs.h29 #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
30 #define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
31 #define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
35 #define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
36 #define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
37 #define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
39 #define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
42 #define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
43 #define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
51 #define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
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Dintel_audio_regs.h12 #define G4X_ELD_VALID REG_BIT(14)
15 #define G4X_ELD_ACK REG_BIT(4)
28 #define IBX_ELD_ACK REG_BIT(4)
30 #define IBX_CP_READY(port) REG_BIT(((port) - 1) * 4 + 1)
31 #define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0)
58 #define AUD_CONFIG_N_VALUE_INDEX REG_BIT(29)
59 #define AUD_CONFIG_N_PROG_ENABLE REG_BIT(28)
81 #define AUD_CONFIG_DISABLE_NCTS REG_BIT(3)
94 #define AUD_M_CTS_M_VALUE_INDEX REG_BIT(21)
95 #define AUD_M_CTS_M_PROG_ENABLE REG_BIT(20)
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/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_gt_regs.h78 #define GEN11_MCR_MULTICAST REG_BIT(31)
168 #define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
176 #define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
179 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
181 #define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
245 #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
353 #define AUX_INV REG_BIT(0)
418 #define TBIMR_FAST_CLIP REG_BIT(5)
421 #define VF_PREFETCH_TLB_DIS REG_BIT(5)
422 #define DIS_OVER_FETCH_CACHE REG_BIT(1)
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Dintel_engine_regs.h48 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
49 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
50 #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
51 #define GEN6_BSD_GO_INDICATOR REG_BIT(4)
52 #define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
53 #define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
54 #define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
74 #define ASYNC_FLIP_PERF_DISABLE REG_BIT(14)
75 #define MI_FLUSH_ENABLE REG_BIT(12)
76 #define TGL_NESTED_BB_EN REG_BIT(12)
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/linux-6.12.1/drivers/gpu/drm/i915/
Di915_reg.h120 #define DEPRESENT REG_BIT(9)
123 #define LMEM_INIT REG_BIT(7)
124 #define DRIVERFLR REG_BIT(31)
126 #define DRIVERFLR_STATUS REG_BIT(31)
328 #define HECI_H_CSR_IE REG_BIT(0)
329 #define HECI_H_CSR_IS REG_BIT(1)
330 #define HECI_H_CSR_IG REG_BIT(2)
331 #define HECI_H_CSR_RDY REG_BIT(3)
332 #define HECI_H_CSR_RST REG_BIT(4)
335 #define HECI_H_GS1_ER_PREP REG_BIT(0)
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/linux-6.12.1/drivers/gpu/drm/xe/tests/
Dxe_rtp_test.c65 .expected_set_bits = REG_BIT(0) | REG_BIT(1),
66 .expected_clr_bits = REG_BIT(0) | REG_BIT(1),
73 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
77 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
85 .expected_set_bits = REG_BIT(0),
86 .expected_clr_bits = REG_BIT(0),
93 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
97 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
105 .expected_set_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2),
106 .expected_clr_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2),
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/linux-6.12.1/drivers/gpu/drm/xe/instructions/
Dxe_mi_commands.h29 #define MI_ARB_ENABLE REG_BIT(0)
37 #define MI_SDI_GGTT REG_BIT(22)
41 REG_BIT(21))
44 #define MI_LRI_LRM_CS_MMIO REG_BIT(19)
45 #define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
47 #define MI_LRI_FORCE_POSTED REG_BIT(12)
51 #define MI_FLUSH_DW_STORE_INDEX REG_BIT(21)
52 #define MI_INVALIDATE_TLB REG_BIT(18)
53 #define MI_FLUSH_DW_CCS REG_BIT(16)
54 #define MI_FLUSH_DW_OP_STOREDW REG_BIT(14)
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