Lines Matching refs:REG_BIT

18 #define   DSB_ENABLE			REG_BIT(31)
19 #define   DSB_BUF_REITERATE		REG_BIT(29)
20 #define   DSB_WAIT_FOR_VBLANK		REG_BIT(28)
21 #define   DSB_WAIT_FOR_LINE_IN		REG_BIT(27)
22 #define   DSB_HALT			REG_BIT(16)
23 #define   DSB_NON_POSTED		REG_BIT(8)
24 #define   DSB_STATUS_BUSY		REG_BIT(0)
26 #define   DSB_MMIO_DEAD_CLOCKS_ENABLE	REG_BIT(31)
32 #define   DSB_POLL_ENABLE		REG_BIT(31)
40 #define   DSB_HP_IDLE_STATUS		REG_BIT(31)
41 #define   DSB_DEWAKE_STATUS		REG_BIT(30)
43 #define   DSB_SAFE_WINDOW_LIVE		REG_BIT(26)
46 #define   DSB_SAFE_WINDOW		REG_BIT(19)
48 #define   DSB_BUSY_DURING_DELAYED_VBLANK	REG_BIT(16)
54 #define   DSB_ATS_FAULT_INT_EN		REG_BIT(20) /* mtl+ */
55 #define   DSB_GTT_FAULT_INT_EN		REG_BIT(19)
56 #define   DSB_RSPTIMEOUT_INT_EN		REG_BIT(18)
57 #define   DSB_POLL_ERR_INT_EN		REG_BIT(17)
58 #define   DSB_PROG_INT_EN		REG_BIT(16)
59 #define   DSB_ATS_FAULT_INT_STATUS	REG_BIT(4) /* mtl+ */
60 #define   DSB_GTT_FAULT_INT_STATUS	REG_BIT(3)
61 #define   DSB_RSPTIMEOUT_INT_STATUS	REG_BIT(2)
62 #define   DSB_POLL_ERR_INT_STATUS	REG_BIT(1)
63 #define   DSB_PROG_INT_STATUS		REG_BIT(0)
66 #define   DSB_RM_CLAIM_TIMEOUT		REG_BIT(31)
67 #define   DSB_RM_READY_TIMEOUT		REG_BIT(30)
74 #define   DSB_ENABLE_DEWAKE		REG_BIT(31)
78 #define   DSB_MMIOGEN_DEWAKE_DIS	REG_BIT(31)
79 #define   DSB_FORCE_DEWAKE		REG_BIT(23)
80 #define   DSB_BLOCK_DEWAKE_EXTENSION	REG_BIT(15)
81 #define   DSB_OVERRIDE_DC5_DC6_OK	REG_BIT(7)
86 #define   DSB_FORCE_DMA_SYNC_RESET	REG_BIT(31)
87 #define   DSB_FORCE_VTD_ENGIE_RESET	REG_BIT(30)
88 #define   DSB_DISABLE_IPC_DEMOTE	REG_BIT(29)
89 #define   DSB_SKIP_WAITS_EN		REG_BIT(23)
90 #define   DSB_EXTEND_HP_IDLE		REG_BIT(16)
91 #define   DSB_CTRL_WAIT_SAFE_WINDOW	REG_BIT(15)
92 #define   DSB_CTRL_NO_WAIT_VBLANK	REG_BIT(14)
93 #define   DSB_INST_WAIT_SAFE_WINDOW	REG_BIT(7)
94 #define   DSB_INST_NO_WAIT_VBLANK	REG_BIT(6)
95 #define   DSB_MMIOGEN_DEWAKE_DIS_CHICKEN	REG_BIT(2)
96 #define   DSB_DISABLE_MMIO_COUNT_FOR_INDEXED	REG_BIT(0)