Lines Matching refs:REG_BIT
120 #define DEPRESENT REG_BIT(9)
123 #define LMEM_INIT REG_BIT(7)
124 #define DRIVERFLR REG_BIT(31)
126 #define DRIVERFLR_STATUS REG_BIT(31)
328 #define HECI_H_CSR_IE REG_BIT(0)
329 #define HECI_H_CSR_IS REG_BIT(1)
330 #define HECI_H_CSR_IG REG_BIT(2)
331 #define HECI_H_CSR_RDY REG_BIT(3)
332 #define HECI_H_CSR_RST REG_BIT(4)
335 #define HECI_H_GS1_ER_PREP REG_BIT(0)
345 #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
390 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
393 #define CLAIM_ER_CLR REG_BIT(31)
394 #define CLAIM_ER_OVERFLOW REG_BIT(16)
571 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
575 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
647 #define ILK_FBCQ_DIS REG_BIT(22)
648 #define ILK_PABSTRETCH_DIS REG_BIT(21)
649 #define ILK_SABSTRETCH_DIS REG_BIT(20)
662 #define IPS_ENABLE REG_BIT(31)
663 #define IPS_FALSE_COLOR REG_BIT(4)
993 #define PROCHOT_MASK REG_BIT(0)
994 #define THERMAL_LIMIT_MASK REG_BIT(1)
995 #define RATL_MASK REG_BIT(5)
996 #define VR_THERMALERT_MASK REG_BIT(6)
997 #define VR_TDC_MASK REG_BIT(7)
998 #define POWER_LIMIT_4_MASK REG_BIT(8)
999 #define POWER_LIMIT_1_MASK REG_BIT(10)
1000 #define POWER_LIMIT_2_MASK REG_BIT(11)
1026 #define DARBF_GATING_DIS REG_BIT(27)
1027 #define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
1028 #define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
1029 #define PWM2_GATING_DIS REG_BIT(14)
1030 #define PWM1_GATING_DIS REG_BIT(13)
1033 #define TGL_VRH_GATING_DIS REG_BIT(31)
1034 #define DPT_GATING_DIS REG_BIT(22)
1040 #define DPCE_GATING_DIS REG_BIT(17)
1048 #define CURSOR_GATING_DIS REG_BIT(28)
1058 #define PIPEDMC_GATING_DIS REG_BIT(12)
1304 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
1305 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
1306 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
1407 #define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
1411 #define PFIT_ENABLE REG_BIT(31)
1425 #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
1428 #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
1429 #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
1586 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
1589 #define TRANSCONF_ENABLE REG_BIT(31)
1590 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
1591 #define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
1592 #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
1595 #define TRANSCONF_PIPE_LOCKED REG_BIT(25)
1596 #define TRANSCONF_FORCE_BORDER REG_BIT(25)
1597 #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
1621 #define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
1624 #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
1625 #define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
1626 #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
1627 #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
1632 #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
1638 #define TRANSCONF_DITHER_EN REG_BIT(4)
1706 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
1710 #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
1711 #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
1712 #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
1713 #define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
1714 #define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
1715 #define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
1716 #define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
1717 #define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
1718 #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
1719 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
1731 #define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
1750 #define PIPE_STATUS_UNDERRUN REG_BIT(31)
1751 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
1752 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
1753 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
1756 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
1757 #define PIPEB_HLINE_INT_EN REG_BIT(28)
1758 #define PIPEB_VBLANK_INT_EN REG_BIT(27)
1759 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
1760 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
1761 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
1762 #define PIPE_PSR_INT_EN REG_BIT(22)
1763 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
1764 #define PIPEA_HLINE_INT_EN REG_BIT(20)
1765 #define PIPEA_VBLANK_INT_EN REG_BIT(19)
1766 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
1767 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
1768 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
1769 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
1770 #define PIPEC_HLINE_INT_EN REG_BIT(12)
1771 #define PIPEC_VBLANK_INT_EN REG_BIT(11)
1772 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
1773 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
1774 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
1779 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
1780 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
1781 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
1782 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
1783 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
1784 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
1785 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
1786 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
1787 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
1788 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
1789 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
1790 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
1793 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
1794 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
1795 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
1796 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
1797 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
1798 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
1799 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
1800 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
1801 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
1802 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
1803 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
1804 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
2035 #define WM_LP_ENABLE REG_BIT(31)
2049 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
2191 #define PF_ENABLE REG_BIT(31)
2230 #define PS_SCALER_EN REG_BIT(31)
2231 #define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
2238 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
2241 #define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
2250 #define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
2253 #define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
2256 #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
2257 #define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
2258 #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
2259 #define PS_PWRUP_PROGRESS REG_BIT(17)
2260 #define PS_V_FILTER_BYPASS REG_BIT(8)
2261 #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
2268 #define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
2270 #define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
2272 #define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
2274 #define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
2282 #define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
2354 #define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
2503 #define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
2504 #define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
2505 #define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
2506 #define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
2507 #define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
2508 #define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
2509 #define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */
2510 #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
2511 #define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */
2512 #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
2513 #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
2514 #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
2515 #define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
2516 #define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
2517 #define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
2518 #define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
2519 #define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
2520 #define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
2521 #define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
2522 #define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
2523 #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
2524 #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
2525 #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */
2526 #define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */
2527 #define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */
2528 #define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */
2529 #define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */
2530 #define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */
2531 #define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */
2532 #define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */
2533 #define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */
2534 #define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */
2535 #define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */
2536 #define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */
2538 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
2539 #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
2540 #define GEN8_PIPE_VSYNC REG_BIT(1)
2541 #define GEN8_PIPE_VBLANK REG_BIT(0)
2559 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
2566 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
2567 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
2568 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
2569 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
2570 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
2571 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
2572 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
2573 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
2574 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
2575 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
2576 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
2582 #define XELPDP_RM_TIMEOUT REG_BIT(29)
2583 #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
2584 #define GEN8_DE_MISC_GSE REG_BIT(27)
2585 #define GEN8_DE_EDP_PSR REG_BIT(19)
2586 #define XELPDP_PMDEMAND_RSP REG_BIT(3)
2609 #define DG1_MSTR_IRQ REG_BIT(31)
2610 #define DG1_MSTR_TILE(t) REG_BIT(t)
2627 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
2634 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
2653 #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
2655 #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
2657 #define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
2659 #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
2663 #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
2664 #define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
2665 #define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
2666 #define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
2667 #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
2668 #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
2678 #define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
2685 #define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
2689 #define ILK_ELPIN_409_SELECT REG_BIT(25)
2690 #define ILK_DPARB_GATE REG_BIT(22)
2691 #define ILK_VSDPFD_FULL REG_BIT(21)
2694 #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
2695 #define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
2696 #define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
2697 #define IVB_PIPE_C_DISABLE REG_BIT(28)
2698 #define ILK_HDCP_DISABLE REG_BIT(25)
2699 #define ILK_eDP_A_DISABLE REG_BIT(24)
2700 #define HSW_CDCLK_LIMIT REG_BIT(24)
2701 #define ILK_DESKTOP REG_BIT(23)
2702 #define HSW_CPU_SSC_ENABLE REG_BIT(21)
2705 #define HSW_REF_CLK_SELECT REG_BIT(1)
2708 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
2709 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
2710 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8)
2711 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7)
2712 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5)
2715 #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
2716 #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
2719 #define IGNORE_KVMR_PIPE_A REG_BIT(23)
2720 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
2721 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
2722 #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
2723 #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
2724 #define FORCE_ARB_IDLE_PLANES REG_BIT(14)
2725 #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
2726 #define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
2729 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
2732 #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
2733 #define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27)
2734 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
2735 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
2736 #define GLK_CL2_PWR_DOWN REG_BIT(12)
2737 #define GLK_CL1_PWR_DOWN REG_BIT(11)
2738 #define GLK_CL0_PWR_DOWN REG_BIT(10)
2741 #define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
2742 #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
2743 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
2746 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
2763 #define HSW_FBCQ_DIS REG_BIT(22)
2764 #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
2765 #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
2771 #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
2789 #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
2790 #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
2793 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
2794 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
2795 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
2796 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
2797 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
2798 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
2799 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
2800 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
2801 #define DP_FEC_BS_JITTER_WA REG_BIT(15)
2802 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
2803 #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
2804 #define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
2807 #define DISP_FBC_MEMORY_WAKE REG_BIT(31)
2808 #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
2809 #define DISP_FBC_WM_DIS REG_BIT(15)
2812 #define DISP_DATA_PARTITION_5_6 REG_BIT(6)
2813 #define DISP_IPC_ENABLE REG_BIT(3)
2824 #define BW_BUDDY_DISABLE REG_BIT(31)
2835 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
2836 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
2839 #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
2840 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
2841 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
2842 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
2843 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
2844 #define ICL_DELAY_PMRSP REG_BIT(22)
2845 #define DISABLE_FLR_SRC REG_BIT(15)
2846 #define MASK_WAKEMEM REG_BIT(13)
2847 #define DDI_CLOCK_REG_ACCESS REG_BIT(7)
2850 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
2851 #define DCPR_MASK_LPMODE REG_BIT(26)
2852 #define DCPR_SEND_RESP_IMM REG_BIT(25)
2853 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
2856 #define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
2897 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
2898 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
2899 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
2900 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
2901 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
2997 #define SDE_PICAINTERRUPT REG_BIT(31)
2999 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
3000 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
3001 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
3328 #define TRANS_ENABLE REG_BIT(31)
3329 #define TRANS_STATE_ENABLE REG_BIT(30)
3345 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
3346 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
3351 #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
3352 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
3355 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
3356 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
3361 #define INVERT_DDIE_HPD REG_BIT(28)
3362 #define INVERT_DDID_HPD_MTP REG_BIT(27)
3363 #define INVERT_TC4_HPD REG_BIT(26)
3364 #define INVERT_TC3_HPD REG_BIT(25)
3365 #define INVERT_TC2_HPD REG_BIT(24)
3366 #define INVERT_TC1_HPD REG_BIT(23)
3377 #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
3403 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
3407 #define TRANS_DP_AUDIO_ONLY REG_BIT(26)
3408 #define TRANS_DP_ENH_FRAMING REG_BIT(18)
3414 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
3415 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
3422 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
3423 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
3424 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
3525 #define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
3526 #define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
3555 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
3557 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
3571 #define POWER_SETUP_I1_WATTS REG_BIT(31)
3773 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
3780 #define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
3788 #define TRANS_DDI_HDCP_SELECT REG_BIT(5)
3805 #define PORT_SYNC_MODE_ENABLE REG_BIT(4)
3810 #define DISABLE_DPT_CLK_GATING REG_BIT(1)
3859 #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
3860 #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
3870 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
4086 #define CDCLK_SQUASH_ENABLE REG_BIT(31)
4160 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
4186 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
4217 #define PLL_ENABLE REG_BIT(31)
4218 #define PLL_LOCK REG_BIT(30)
4219 #define PLL_POWER_ENABLE REG_BIT(27)
4220 #define PLL_POWER_STATE REG_BIT(26)
4366 #define DC_STATE_EN_DC3CO REG_BIT(30)
4367 #define DC_STATE_DC3CO_STATUS REG_BIT(29)
4368 #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
4369 #define HOLD_PHY_PG1_LATCH REG_BIT(20)
4441 #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
4454 #define SGSI_SIDECLK_DIS REG_BIT(17)
4455 #define SGGI_DIS REG_BIT(15)
4456 #define SGR_DIS REG_BIT(13)
4493 #define TCSS_DDI_STATUS_READY REG_BIT(2)
4494 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
4495 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
4506 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
4509 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
4514 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)