Lines Matching refs:REG_BIT
13 #define EXITLINE_ENABLE REG_BIT(31)
27 #define EDP_PSR_ENABLE REG_BIT(31)
28 #define BDW_PSR_SINGLE_FRAME REG_BIT(30)
29 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */
30 #define EDP_PSR_LINK_STANDBY REG_BIT(27)
40 #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12)
41 #define EDP_PSR_TP_MASK REG_BIT(11)
44 #define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */
74 #define TGL_PSR_ERROR REG_BIT(2)
75 #define TGL_PSR_POST_EXIT REG_BIT(1)
76 #define TGL_PSR_PRE_ENTRY REG_BIT(0)
93 #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT REG_BIT(11)
119 #define EDP_PSR_STATUS_AUX_ERROR REG_BIT(15)
120 #define EDP_PSR_STATUS_AUX_SENDING REG_BIT(12)
121 #define EDP_PSR_STATUS_SENDING_IDLE REG_BIT(9)
122 #define EDP_PSR_STATUS_SENDING_TP2_TP3 REG_BIT(8)
123 #define EDP_PSR_STATUS_SENDING_TP1 REG_BIT(4)
137 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28)
138 #define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27)
139 #define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26)
140 #define EDP_PSR_DEBUG_MASK_HPD REG_BIT(25)
141 #define EDP_PSR_DEBUG_MASK_FBC_MODIFY REG_BIT(24)
142 #define EDP_PSR_DEBUG_MASK_PRIMARY_FLIP REG_BIT(23) /* hsw */
143 #define EDP_PSR_DEBUG_MASK_HDCP_ENABLE REG_BIT(22) /* hsw/bdw */
144 #define EDP_PSR_DEBUG_MASK_SPRITE_ENABLE REG_BIT(21) /* hsw */
145 #define EDP_PSR_DEBUG_MASK_CURSOR_MOVE REG_BIT(20) /* hsw */
146 #define EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT REG_BIT(19) /* hsw */
147 #define EDP_PSR_DEBUG_MASK_DPST_PHASE_IN REG_BIT(18) /* hsw */
148 #define EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN REG_BIT(17)
149 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE REG_BIT(16) /* hsw-skl */
150 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN REG_BIT(15) /* skl+ */
151 #define EDP_PSR_DEBUG_RFB_UPDATE_SENT REG_BIT(2) /* bdw */
152 #define EDP_PSR_DEBUG_ENTRY_COMPLETION REG_BIT(1) /* hsw/bdw */
157 #define EDP_PSR2_ENABLE REG_BIT(31)
158 #define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */
159 #define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28)
162 #define LNL_EDP_PSR2_SU_REGION_ET_ENABLE REG_BIT(27)
163 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
164 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */
203 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17)
204 #define PSR_EVENT_PSR2_DISABLED REG_BIT(16)
205 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15)
206 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN REG_BIT(14)
207 #define PSR_EVENT_GRAPHICS_RESET REG_BIT(12)
208 #define PSR_EVENT_PCH_INTERRUPT REG_BIT(11)
209 #define PSR_EVENT_MEMORY_UP REG_BIT(10)
210 #define PSR_EVENT_FRONT_BUFFER_MODIFY REG_BIT(9)
211 #define PSR_EVENT_WD_TIMER_EXPIRE REG_BIT(8)
212 #define PSR_EVENT_PIPE_REGISTERS_UPDATE REG_BIT(6)
213 #define PSR_EVENT_REGISTER_UPDATE REG_BIT(5) /* Reserved in ICL+ */
214 #define PSR_EVENT_HDCP_ENABLE REG_BIT(4)
215 #define PSR_EVENT_KVMR_SESSION_ENABLE REG_BIT(3)
216 #define PSR_EVENT_VBI_ENABLE REG_BIT(2)
217 #define PSR_EVENT_LPSP_MODE_EXIT REG_BIT(1)
218 #define PSR_EVENT_PSR_DISABLE REG_BIT(0)
237 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
242 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
243 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
244 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
249 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
250 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
251 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
260 #define ALPM_CTL_ALPM_ENABLE REG_BIT(31)
261 #define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30)
262 #define ALPM_CTL_LOBF_ENABLE REG_BIT(29)
263 #define ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE REG_BIT(28)
264 #define ALPM_CTL_KEEP_FEC_ENABLE_FOR_AUX_WAKE_SLEEP REG_BIT(27)
265 #define ALPM_CTL_RESTORE_OCCURED REG_BIT(26)
266 #define ALPM_CTL_RESTORE_TO_SLEEP REG_BIT(25)
267 #define ALPM_CTL_RESTORE_TO_DEEP_SLEEP REG_BIT(24)
273 #define ALPM_CTL_AUX_WAKE_SLEEP_HOLD_ENABLE REG_BIT(20)
292 #define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR REG_BIT(4)
299 #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31)
310 #define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31)