Lines Matching refs:REG_BIT
50 #define MCR_MULTICAST REG_BIT(31)
66 #define LE_SCF_MASK REG_BIT(14)
72 #define LE_RSC_MASK REG_BIT(7)
74 #define LE_AOM_MASK REG_BIT(6)
87 #define CG_DIS_CNTLBUS REG_BIT(6)
95 #define AUX_INV REG_BIT(0)
104 #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10)
107 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
108 #define DIS_CLIP_NEGATIVE_BOUNDING_BOX REG_BIT(6)
111 #define TBIMR_FAST_CLIP REG_BIT(5)
114 #define DIS_TE_AUTOSTRIP REG_BIT(31)
116 #define DIS_MESH_PARTIAL_AUTOSTRIP REG_BIT(16)
117 #define DIS_MESH_AUTOSTRIP REG_BIT(15)
120 #define DIS_PARTIAL_AUTOSTRIP REG_BIT(9)
121 #define DIS_AUTOSTRIP REG_BIT(6)
122 #define DIS_OVER_FETCH_CACHE REG_BIT(1)
123 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
135 #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
138 #define DISABLE_BOTTOM_CLIP_RECTANGLE_TEST REG_BIT(14)
141 #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
142 #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
145 #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
148 #define FLSH_IGNORES_PSD REG_BIT(10)
149 #define FD_END_COLLECT REG_BIT(5)
160 #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6)
164 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
165 #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
166 #define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
167 #define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
170 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
178 #define XE2_VFG_TED_CREDIT_INTERFACE_DISABLE REG_BIT(13)
181 #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4)
185 #define SQCNT1_PMON_ENABLE REG_BIT(30)
186 #define SQCNT1_OABPC REG_BIT(29)
187 #define ENFORCE_RAR REG_BIT(23)
190 #define EN_32B_ACCESS REG_BIT(30)
193 #define XE2_FLAT_CCS_ENABLE REG_BIT(0)
202 #define L3CMPCTRL REG_BIT(23)
203 #define ENCOMPPERFFIX REG_BIT(18)
207 #define CFEG_WMTP_DISABLE REG_BIT(20)
240 #define GRDOM_GUC REG_BIT(3)
241 #define GRDOM_FULL REG_BIT(0)
244 #define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
247 #define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
250 #define VFUNIT_CLKGATE_DIS REG_BIT(20)
251 #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
252 #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
253 #define GAMEDIA_CLKGATE_DIS REG_BIT(11)
254 #define HSUNIT_CLKGATE_DIS REG_BIT(8)
255 #define VSUNIT_CLKGATE_DIS REG_BIT(3)
258 #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
259 #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
260 #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
261 #define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
262 #define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
263 #define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
264 #define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
265 #define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
266 #define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
267 #define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
268 #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
269 #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
272 #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
273 #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
274 #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
275 #define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
276 #define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
277 #define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
278 #define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
279 #define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
280 #define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
281 #define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
282 #define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
283 #define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
284 #define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
285 #define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
286 #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
287 #define LTCDD_CLKGATE_DIS REG_BIT(10)
290 #define L3_CR2X_CLKGATE_DIS REG_BIT(17)
291 #define L3_CLKGATE_DIS REG_BIT(16)
292 #define NODEDSS_CLKGATE_DIS REG_BIT(12)
293 #define MSCUNIT_CLKGATE_DIS REG_BIT(10)
294 #define RCCUNIT_CLKGATE_DIS REG_BIT(7)
295 #define SARBUNIT_CLKGATE_DIS REG_BIT(5)
296 #define SBEUNIT_CLKGATE_DIS REG_BIT(4)
299 #define VSUNIT_CLKGATE2_DIS REG_BIT(19)
302 #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
303 #define GWUNIT_CLKGATE_DIS REG_BIT(16)
306 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
309 #define RTFUNIT_CLKGATE_DIS REG_BIT(18)
312 #define DFR_DISABLE REG_BIT(9)
322 #define RC_CTL_HW_ENABLE REG_BIT(31)
323 #define RC_CTL_TO_MODE REG_BIT(28)
324 #define RC_CTL_RC6_ENABLE REG_BIT(18)
331 #define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31)
332 #define ARAT_EXPIRED_INTRMSK REG_BIT(9)
337 #define RENDER_POWERGATE_ENABLE REG_BIT(0)
338 #define MEDIA_POWERGATE_ENABLE REG_BIT(1)
339 #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
340 #define VDN_MFXVDENC_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
344 #define CTC_SOURCE_DIVIDE_LOGIC REG_BIT(0)
352 #define XEHPC_OVRLSCCC REG_BIT(0)
358 #define L3_UPPER_LKUP_MASK REG_BIT(23)
359 #define L3_UPPER_GLBGO_MASK REG_BIT(22)
362 #define L3_UPPER_IDX_ESC_MASK REG_BIT(16)
363 #define L3_LKUP_MASK REG_BIT(7)
365 #define L3_GLBGO_MASK REG_BIT(6)
371 #define L3_ESC_MASK REG_BIT(0)
375 #define XEHP_LNESPARE REG_BIT(19)
378 #define COMPMEMRD256BOVRFETCHEN REG_BIT(20)
381 #define COMPPWOVERFETCHEN REG_BIT(28)
384 #define RWFLUSHALLEN REG_BIT(17)
390 #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
405 #define TRANSIENT_FLUSH_REQUEST REG_BIT(0)
414 #define FORCE_MISS_FTLB REG_BIT(3)
417 #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
418 #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
419 #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
422 #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
423 #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
426 #define LMEM_EN REG_BIT(31)
430 #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0)
436 #define ENABLE_SMALLPL REG_BIT(15)
437 #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
438 #define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
439 #define INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
442 #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
443 #define CLEAR_OPTIMIZATION_DISABLE REG_BIT(6)
446 #define DISABLE_ECC REG_BIT(5)
447 #define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
450 #define DISABLE_GRF_CLEAR REG_BIT(13)
451 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
452 #define DISABLE_TDL_PUSH REG_BIT(9)
453 #define DIS_PICK_2ND_EU REG_BIT(7)
454 #define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
459 #define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14)
460 #define DIS_FIX_EOT1_FLUSH REG_BIT(9)
463 #define STK_ID_RESTRICT REG_BIT(12)
464 #define SLM_WMTP_RESTORE REG_BIT(11)
467 #define UGM_BACKUP_MODE REG_BIT(13)
468 #define MDQ_ARBITRATION_MODE REG_BIT(12)
469 #define STALL_DOP_GATING_DISABLE REG_BIT(5)
470 #define EARLY_EOT_DIS REG_BIT(1)
473 #define DISABLE_READ_SUPPRESSION REG_BIT(15)
474 #define DISABLE_EARLY_READ REG_BIT(14)
475 #define ENABLE_LARGE_GRF_MODE REG_BIT(12)
476 #define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
477 #define DISABLE_TDL_SVHS_GATING REG_BIT(1)
478 #define DISABLE_DOP_GATING REG_BIT(0)
481 #define DIS_NULL_QUERY REG_BIT(10)
484 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31)
488 #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
491 #define DISABLE_D8_D16_COASLESCE REG_BIT(30)
492 #define WR_REQ_CHAINING_DIS REG_BIT(26)
493 #define TGM_WRITE_EOM_FORCE REG_BIT(17)
494 #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
495 #define SEQUENTIAL_ACCESS_UPGRADE_DISABLE REG_BIT(13)
498 #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32)
499 #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
500 #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32)
501 #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32)
502 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
503 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
505 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
511 #define RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
512 #define RCU_MODE_CCS_ENABLE REG_BIT(0)
547 #define PROCHOT_MASK REG_BIT(0)
548 #define THERMAL_LIMIT_MASK REG_BIT(1)
549 #define RATL_MASK REG_BIT(5)
550 #define VR_THERMALERT_MASK REG_BIT(6)
551 #define VR_TDC_MASK REG_BIT(7)
552 #define POWER_LIMIT_4_MASK REG_BIT(8)
553 #define POWER_LIMIT_1_MASK REG_BIT(10)
554 #define POWER_LIMIT_2_MASK REG_BIT(11)
566 #define INTR_GSC REG_BIT(31)
567 #define INTR_GUC REG_BIT(25)
568 #define INTR_MGUC REG_BIT(24)
569 #define INTR_BCS8 REG_BIT(23)
570 #define INTR_BCS(x) REG_BIT(15 - (x))
571 #define INTR_CCS(x) REG_BIT(4 + (x))
572 #define INTR_RCS0 REG_BIT(0)
573 #define INTR_VECS(x) REG_BIT(31 - (x))
574 #define INTR_VCS(x) REG_BIT(x)
586 #define INTR_DATA_VALID REG_BIT(31)
610 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
611 #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8)
612 #define GSC_ER_COMPLETE REG_BIT(5)
613 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4)
614 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
615 #define GT_RENDER_USER_INTERRUPT REG_BIT(0)