Lines Matching refs:REG_BIT
61 #define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
62 #define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
63 #define IDLE_MSG_DISABLE REG_BIT(0)
91 #define ENABLE_SEMAPHORE_POLL_BIT REG_BIT(13)
105 #define GHWSP_CSB_REPORT_DIS REG_BIT(15)
106 #define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14)
107 #define CS_PRIORITY_MEM_READ REG_BIT(7)
110 #define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
113 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
114 #define REPLAY_MODE_GRANULARITY REG_BIT(0)
122 #define BCS_SWCTRL_DISABLE_256B REG_BIT(2)
133 #define CTX_CTRL_OAC_CONTEXT_ENABLE REG_BIT(8)
134 #define CTX_CTRL_RUN_ALONE REG_BIT(7)
135 #define CTX_CTRL_INDIRECT_RING_STATE_ENABLE REG_BIT(4)
136 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
137 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
140 #define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
147 #define STOP_RING REG_BIT(8)
153 #define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
174 #define EL_CTRL_LOAD REG_BIT(0)
182 #define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
185 #define CG3DDISHRS_CLKGATE_DIS REG_BIT(5)
188 #define IECPUNIT_CLKGATE_DIS REG_BIT(22)
191 #define ALNUNIT_CLKGATE_DIS REG_BIT(13)
194 #define MFXPIPE_CLKGATE_DIS REG_BIT(3)