Lines Matching refs:REG_BIT

48 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE		REG_BIT(12)
49 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	REG_BIT(10)
50 #define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
51 #define   GEN6_BSD_GO_INDICATOR			REG_BIT(4)
52 #define   GEN6_BSD_SLEEP_INDICATOR		REG_BIT(3)
53 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE		REG_BIT(2)
54 #define   GEN6_PSMI_SLEEP_MSG_DISABLE		REG_BIT(0)
74 #define   ASYNC_FLIP_PERF_DISABLE		REG_BIT(14)
75 #define   MI_FLUSH_ENABLE			REG_BIT(12)
76 #define   TGL_NESTED_BB_EN			REG_BIT(12)
77 #define   MODE_IDLE				REG_BIT(9)
78 #define   STOP_RING				REG_BIT(8)
79 #define   VS_TIMER_DISPATCH			REG_BIT(6)
104 #define   RESET_CTL_CAT_ERROR			REG_BIT(2)
105 #define   RESET_CTL_READY_TO_RESET		REG_BIT(1)
106 #define   RESET_CTL_REQUEST_RESET		REG_BIT(0)
130 #define   ECO_CONSTANT_BUFFER_SR_DISABLE	REG_BIT(4)
131 #define   ECO_GATING_CX_ONLY			REG_BIT(3)
132 #define   GEN6_BLITTER_FBC_NOTIFY		REG_BIT(3)
133 #define   ECO_FLIP_DONE				REG_BIT(0)
182 #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	REG_BIT(0)
183 #define   CTX_CTRL_RS_CTX_ENABLE		REG_BIT(1)
184 #define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	REG_BIT(2)
185 #define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	REG_BIT(3)
186 #define	  GEN12_CTX_CTRL_RUNALONE_MODE		REG_BIT(7)
187 #define	  GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE	REG_BIT(8)
199 #define   GEN12_GFX_PREFETCH_DISABLE		REG_BIT(10)
214 #define   RING_FORCE_TO_NONPRIV_DENY		REG_BIT(30)
235 #define	  EL_CTRL_LOAD				REG_BIT(0)
257 #define   GEN12_HCP_SFC_LOCK_ACK_BIT		REG_BIT(1)
258 #define   GEN12_HCP_SFC_USAGE_BIT		REG_BIT(0)
261 #define   IECPUNIT_CLKGATE_DIS			REG_BIT(22)
264 #define   ALNUNIT_CLKGATE_DIS			REG_BIT(13)
267 #define   MFXPIPE_CLKGATE_DIS			REG_BIT(3)