Lines Matching refs:REG_BIT
21 #define DRB_VALID REG_BIT(0)
25 #define GTCR_INVALIDATE REG_BIT(0)
41 #define GS_MIA_IN_RESET REG_BIT(0)
47 #define GUC_WOPCM_SIZE_LOCKED REG_BIT(0)
51 #define GUC_SHIM_WC_ENABLE REG_BIT(21)
52 #define GUC_ENABLE_MIA_CLOCK_GATING REG_BIT(15)
53 #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA REG_BIT(10)
54 #define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA REG_BIT(9)
55 #define GUC_MSGCH_ENABLE REG_BIT(4)
56 #define GUC_ENABLE_MIA_CACHING REG_BIT(2)
57 #define GUC_ENABLE_READ_CACHE_LOGIC REG_BIT(1)
58 #define GUC_DISABLE_SRAM_INIT_TO_ZEROES REG_BIT(0)
64 #define HUC_LOAD_SUCCESSFUL REG_BIT(0)
78 #define HUC_UKERNEL REG_BIT(9)
79 #define UOS_MOVE REG_BIT(4)
80 #define START_DMA REG_BIT(0)
84 #define HUC_LOADING_AGENT_GUC REG_BIT(1)
85 #define GUC_WOPCM_OFFSET_VALID REG_BIT(0)
89 #define GUC_SEND_TRIGGER REG_BIT(0)
97 #define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
100 #define HUC_FW_VERIFIED REG_BIT(7)
103 #define GT_DOORBELL_ENABLE REG_BIT(0)
116 #define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
118 #define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0)
120 #define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
123 #define GUC_INTR_GUC2HOST REG_BIT(15)
124 #define GUC_INTR_EXEC_ERROR REG_BIT(14)
125 #define GUC_INTR_DISPLAY_EVENT REG_BIT(13)
126 #define GUC_INTR_SEM_SIG REG_BIT(12)
127 #define GUC_INTR_IOMMU2GUC REG_BIT(11)
128 #define GUC_INTR_DOORBELL_RANG REG_BIT(10)
129 #define GUC_INTR_DMA_DONE REG_BIT(9)
130 #define GUC_INTR_FATAL_ERROR REG_BIT(8)
131 #define GUC_INTR_NOTIF_ERROR REG_BIT(7)
132 #define GUC_INTR_SW_INT_6 REG_BIT(6)
133 #define GUC_INTR_SW_INT_5 REG_BIT(5)
134 #define GUC_INTR_SW_INT_4 REG_BIT(4)
135 #define GUC_INTR_SW_INT_3 REG_BIT(3)
136 #define GUC_INTR_SW_INT_2 REG_BIT(2)
137 #define GUC_INTR_SW_INT_1 REG_BIT(1)
138 #define GUC_INTR_SW_INT_0 REG_BIT(0)