Lines Matching refs:REG_BIT

12 #define   FBC_CTL_EN			REG_BIT(31)
13 #define   FBC_CTL_PERIODIC		REG_BIT(30)
16 #define   FBC_CTL_STOP_ON_MOD		REG_BIT(15)
17 #define   FBC_CTL_UNCOMPRESSIBLE	REG_BIT(14) /* i915+ */
18 #define   FBC_CTL_C3_IDLE		REG_BIT(13) /* i945gm only */
24 #define   FBC_CMD_COMPRESS		REG_BIT(0)
26 #define   FBC_STAT_COMPRESSING		REG_BIT(31)
27 #define   FBC_STAT_COMPRESSED		REG_BIT(30)
28 #define   FBC_STAT_MODIFIED		REG_BIT(29)
31 #define   FBC_CTL_FENCE_DBL		REG_BIT(4)
37 #define   FBC_CTL_CPU_FENCE_EN		REG_BIT(1)
43 #define   FBC_MOD_NUM_VALID		REG_BIT(0)
57 #define   DPFC_CTL_EN				REG_BIT(31)
58 #define   DPFC_CTL_PLANE_MASK_G4X		REG_BIT(30) /* g4x-snb */
60 #define   DPFC_CTL_FENCE_EN_G4X			REG_BIT(29) /* g4x-snb */
63 #define   DPFC_CTL_FENCE_EN_IVB			REG_BIT(28) /* ivb+ */
64 #define   DPFC_CTL_PERSISTENT_MODE		REG_BIT(25) /* g4x-snb */
67 #define   DPFC_CTL_FALSE_COLOR			REG_BIT(10) /* ivb+ */
68 #define   DPFC_CTL_SR_EN			REG_BIT(10) /* g4x only */
69 #define   DPFC_CTL_SR_EXIT_DIS			REG_BIT(9) /* g4x only */
78 #define   DPFC_RECOMP_STALL_EN			REG_BIT(27)
92 #define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */
93 #define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */
94 #define   DPFC_CHICKEN_COMP_DUMMY_PIXEL		REG_BIT(14) /* glk+ */
95 #define   DPFC_CHICKEN_FORCE_SLB_INVALIDATION	REG_BIT(13) /* icl+ */
96 #define   DPFC_DISABLE_DUMMY0			REG_BIT(8) /* ivb+ */
99 #define   FBC_STRIDE_OVERRIDE	REG_BIT(15)
104 #define   ILK_FBC_RT_VALID	REG_BIT(0)
105 #define   SNB_FBC_FRONT_BUFFER	REG_BIT(1)
108 #define   SNB_DPFC_FENCE_EN		REG_BIT(29)
117 #define   FBC_REND_NUKE			REG_BIT(2)
118 #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)