Lines Matching refs:REG_BIT
78 #define GEN11_MCR_MULTICAST REG_BIT(31)
168 #define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
176 #define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
179 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
181 #define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
245 #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
353 #define AUX_INV REG_BIT(0)
418 #define TBIMR_FAST_CLIP REG_BIT(5)
421 #define VF_PREFETCH_TLB_DIS REG_BIT(5)
422 #define DIS_OVER_FETCH_CACHE REG_BIT(1)
423 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
438 #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
439 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6)
440 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6)
441 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1)
459 #define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15)
460 #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
461 #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
462 #define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3)
470 #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
473 #define FD_END_COLLECT REG_BIT(5)
489 #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6)
495 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
496 #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
497 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
498 #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
502 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
531 #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4)
536 #define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
537 #define GEN12_SQCNT1_OABPC REG_BIT(29)
538 #define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
541 #define EN_32B_ACCESS REG_BIT(30)
565 #define FBC_LLC_FULLY_OPEN REG_BIT(30)
672 #define XEHPC_GRDOM_BLT8 REG_BIT(31)
673 #define XEHPC_GRDOM_BLT7 REG_BIT(30)
674 #define XEHPC_GRDOM_BLT6 REG_BIT(29)
675 #define XEHPC_GRDOM_BLT5 REG_BIT(28)
676 #define XEHPC_GRDOM_BLT4 REG_BIT(27)
677 #define XEHPC_GRDOM_BLT3 REG_BIT(26)
678 #define XEHPC_GRDOM_BLT2 REG_BIT(25)
679 #define XEHPC_GRDOM_BLT1 REG_BIT(24)
680 #define GEN12_GRDOM_GSC REG_BIT(21)
681 #define GEN11_GRDOM_SFC3 REG_BIT(20)
682 #define GEN11_GRDOM_SFC2 REG_BIT(19)
683 #define GEN11_GRDOM_SFC1 REG_BIT(18)
684 #define GEN11_GRDOM_SFC0 REG_BIT(17)
685 #define GEN11_GRDOM_VECS4 REG_BIT(16)
686 #define GEN11_GRDOM_VECS3 REG_BIT(15)
687 #define GEN11_GRDOM_VECS2 REG_BIT(14)
688 #define GEN11_GRDOM_VECS REG_BIT(13)
689 #define GEN11_GRDOM_MEDIA8 REG_BIT(12)
690 #define GEN11_GRDOM_MEDIA7 REG_BIT(11)
691 #define GEN11_GRDOM_MEDIA6 REG_BIT(10)
692 #define GEN11_GRDOM_MEDIA5 REG_BIT(9)
693 #define GEN11_GRDOM_MEDIA4 REG_BIT(8)
694 #define GEN11_GRDOM_MEDIA3 REG_BIT(7)
695 #define GEN11_GRDOM_MEDIA2 REG_BIT(6)
696 #define GEN11_GRDOM_MEDIA REG_BIT(5)
697 #define GEN11_GRDOM_GUC REG_BIT(3)
698 #define GEN11_GRDOM_BLT REG_BIT(2)
705 #define GEN7_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
706 #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
717 #define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
720 #define VFUNIT_CLKGATE_DIS REG_BIT(20)
721 #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
722 #define GAMEDIA_CLKGATE_DIS REG_BIT(11)
723 #define HSUNIT_CLKGATE_DIS REG_BIT(8)
724 #define VSUNIT_CLKGATE_DIS REG_BIT(3)
731 #define NODEDSS_CLKGATE_DIS REG_BIT(12)
732 #define L3_CLKGATE_DIS REG_BIT(16)
733 #define L3_CR2X_CLKGATE_DIS REG_BIT(17)
736 #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
737 #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
740 #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
741 #define GWUNIT_CLKGATE_DIS REG_BIT(16)
744 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
747 #define RTFUNIT_CLKGATE_DIS REG_BIT(18)
779 #define GEN12_MEDIA_FREQ_RATIO REG_BIT(13)
868 #define GEN9_RENDER_PG_ENABLE REG_BIT(0)
869 #define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
870 #define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
871 #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
872 #define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
905 #define IDLE_MSG_DISABLE REG_BIT(0)
941 #define GEN12_BUS_HASH_CTL_BIT_EXC REG_BIT(7)
942 #define GEN9_GAPS_TSV_CREDIT_DISABLE REG_BIT(7)
947 #define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
978 #define XEHP_LNESPARE REG_BIT(19)
995 #define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
998 #define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
1010 #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
1068 #define FORCE_MISS_FTLB REG_BIT(3)
1071 #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
1072 #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
1073 #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
1076 #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
1077 #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
1108 #define ENABLE_SMALLPL REG_BIT(15)
1109 #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
1110 #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
1111 #define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3)
1112 #define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
1115 #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
1116 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8)
1117 #define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4)
1118 #define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
1121 #define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
1122 #define DISABLE_ECC REG_BIT(5)
1123 #define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
1129 #define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
1130 #define DISABLE_PREFETCH_INTO_IC REG_BIT(3)
1136 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
1137 #define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
1138 #define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
1139 #define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
1146 #define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9)
1149 #define FLOW_CONTROL_ENABLE REG_BIT(15)
1150 #define UGM_BACKUP_MODE REG_BIT(13)
1151 #define MDQ_ARBITRATION_MODE REG_BIT(12)
1152 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
1153 #define STALL_DOP_GATING_DISABLE REG_BIT(5)
1155 #define DISABLE_EARLY_EOT REG_BIT(1)
1160 #define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
1161 #define GEN12_DISABLE_EARLY_READ REG_BIT(14)
1162 #define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
1163 #define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
1164 #define XELPG_DISABLE_TDL_SVHS_GATING REG_BIT(1)
1165 #define GEN12_DISABLE_DOP_GATING REG_BIT(0)
1168 #define DIS_NULL_QUERY REG_BIT(10)
1177 #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
1186 #define DISABLE_D8_D16_COASLESCE REG_BIT(30)
1187 #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
1189 #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32)
1190 #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
1191 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
1192 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
1194 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
1427 #define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
1428 #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
1448 #define BCS_SRC_Y REG_BIT(0)
1449 #define BCS_DST_Y REG_BIT(1)