| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-rk3568.c | 217 PNAME(mux_pll_p) = { "xin24m" };
218 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
230 PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
231 PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
232 PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
233 PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
234 PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
235 PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
236 PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
237 PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
[all …]
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| D | clk-rv1126.c | 145 PNAME(mux_pll_p) = { "xin24m" };
148 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
149 PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
150 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
151 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
152 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
156 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
161 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
162 PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
163 PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
[all …]
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| D | clk-rk3576.c | 278 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
279 PNAME(mux_24m_32k_p) = { "xin24m", "xin_osc0_div" };
280 PNAME(mux_armclkl_p) = { "xin24m", "pll_lpll", "lpll" };
281 PNAME(mux_armclkb_p) = { "xin24m", "pll_bpll", "bpll" };
282 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
283 PNAME(cpll_24m_p) = { "cpll", "xin24m" };
287 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
288 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
289 PNAME(gpll_cpll_aupll_24m_p) = { "gpll", "cpll", "aupll", "xin24m" };
295 PNAME(gpll_cpll_vpll_aupll_24m_p) = { "gpll", "cpll", "vpll", "aupll", "xin24m" };
[all …]
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| D | clk-rk3588.c | 444 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
445 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
446 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
447 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
449 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
454 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"};
458 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
467 PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" };
468 PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" };
469 PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" };
[all …]
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| D | clk-rk3368.c | 90 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
116 PNAME(mux_edp_24m_p) = { "xin24m", "dummy" };
117 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
118 PNAME(mux_usbphy480m_p) = { "usbotg_out", "xin24m" };
121 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
122 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
123 PNAME(mux_uart2_p) = { "uart2_src", "xin24m" };
124 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
125 PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
127 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "usbphy_480m", "xin24m" };
[all …]
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| D | clk-rk3128.c | 130 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
134 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
142 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
143 PNAME(mux_clk_cif_out_src_p) = { "clk_cif_src", "xin24m" };
151 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
152 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
153 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
156 PNAME(mux_sclk_sfc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
205 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
291 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
[all …]
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| D | clk-rk3399.c | 109 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
142 "xin24m" };
148 "upll", "xin24m" };
150 "ppll", "upll", "xin24m" };
156 "xin24m" };
163 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
165 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
166 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
167 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
184 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
[all …]
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| D | clk-rk3288.c | 192 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
203 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
208 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
209 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
210 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
211 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
212 PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
213 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
216 PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
358 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
[all …]
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| D | clk-px30.c | 137 PNAME(mux_pll_p) = { "xin24m"};
138 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
147 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
149 PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" };
150 PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"};
162 PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" };
168 PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" };
169 PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
170 PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
178 PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" };
[all …]
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| D | clk-rv1108.c | 119 PNAME(mux_pll_p) = { "xin24m", "xin24m"};
122 PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
123 PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
130 PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
132 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
133 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
134 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
140 PNAME(mux_wifi_src_p) = { "gpll", "xin24m" };
142 PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" };
148 PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" };
[all …]
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| D | clk-rk3228.c | 132 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
137 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
138 PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
144 PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
146 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
160 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
161 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
162 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
216 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
329 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
[all …]
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| D | clk-rk3036.c | 115 PNAME(mux_pll_p) = { "xin24m", "xin24m" };
121 PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
124 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
126 PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
130 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
131 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
132 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
177 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
386 /* xin24m gates */
387 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
[all …]
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| D | clk-rk3328.c | 143 PNAME(mux_pll_p) = { "xin24m" };
148 PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
157 "xin24m", "usb480m" };
164 PNAME(mux_hdmiphy_p) = { "hdmi_phy", "xin24m" };
166 "xin24m" };
188 "xin24m" };
191 "xin24m" };
194 "xin24m" };
197 "xin24m" };
203 PNAME(mux_ref_usb3otg_src_p) = { "xin24m",
[all …]
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| D | clk-rk3308.c | 122 PNAME(mux_pll_p) = { "xin24m" };
123 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
126 PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
128 PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" };
129 PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
131 PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
137 PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
146 PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_usbphy_ref_src" };
286 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
308 GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
[all …]
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| D | clk-rk3188.c | 198 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
204 PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
207 PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
208 PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
209 PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
210 PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
343 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
349 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
351 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
372 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | rockchip,px30-cru.yaml | 25 - "xin24m" - crystal input - required
54 - const: xin24m
104 clocks = <&xin24m>;
105 clock-names = "xin24m";
114 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
115 clock-names = "xin24m", "gpll";
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| D | rockchip,rk3036-cru.yaml | 25 - "xin24m" - crystal input - required
47 const: xin24m
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| D | rockchip,rk3228-cru.yaml | 25 - "xin24m" - crystal input - required
49 const: xin24m
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| D | rockchip,rk3308-cru.yaml | 25 - "xin24m" - crystal input - required
51 const: xin24m
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| D | rockchip,rk3368-cru.yaml | 25 - "xin24m" - crystal input - required
53 const: xin24m
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| D | rockchip,rk3188-cru.yaml | 25 - "xin24m" - crystal input - required
53 const: xin24m
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| D | rockchip,rv1108-cru.yaml | 25 - "xin24m" - crystal input - required
50 const: xin24m
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| D | rockchip,rk3399-cru.yaml | 25 - "xin24m" - crystal input - required,
52 const: xin24m
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| D | rockchip,rk3288-cru.yaml | 32 - "xin24m" - crystal input - required,
60 const: xin24m
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| D | rockchip,rk3576-cru.yaml | 38 - const: xin24m
|