clk/rockchip/clk-rv1108.c

119 PNAME(mux_pll_p)		= { "xin24m", "xin24m"};
122 PNAME(mux_usb480m_pre_p)	= { "usbphy", "xin24m" };
123 PNAME(mux_hdmiphy_phy_p)	= { "hdmiphy", "xin24m" };
130 PNAME(mux_mmc_src_p)		= { "dpll", "gpll", "xin24m", "usb480m" };
132 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
133 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
134 PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
140 PNAME(mux_wifi_src_p)		= { "gpll", "xin24m" };
142 PNAME(mux_cifout_p)		= { "sclk_cifout_src", "xin24m" };
148 PNAME(mux_dclk_hdmiphy_p)	= { "hdmiphy", "xin24m" };
150 PNAME(mux_hdmi_cec_src_p)		= { "dpll", "gpll", "xin24m" };
291 	GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
305 	COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0,
466 	GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0,
485 	GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED,
498 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
555 	GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
557 	GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED,
649 	COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
654 	COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
684 	GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
743 	GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS),