clk/rockchip/clk-rk3368.c

90 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
116 PNAME(mux_edp_24m_p)		= { "xin24m", "dummy" };
117 PNAME(mux_vip_out_p)		= { "vip_src", "xin24m" };
118 PNAME(mux_usbphy480m_p)		= { "usbotg_out", "xin24m" };
121 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
122 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
123 PNAME(mux_uart2_p)		= { "uart2_src", "xin24m" };
124 PNAME(mux_uart3_p)		= { "uart3_src", "uart3_frac", "xin24m" };
125 PNAME(mux_uart4_p)		= { "uart4_src", "uart4_frac", "xin24m" };
127 PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "usbphy_480m", "xin24m" };
279 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
323 	GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
454 	GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
471 	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
501 	GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
514 	GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
529 	GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
565 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
577 	COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
835 …GATE(SCLK_TIMER15, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS…
836 …GATE(SCLK_TIMER14, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS…
837 	GATE(SCLK_TIMER13, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS),
838 	GATE(SCLK_TIMER12, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS),
839 	GATE(SCLK_TIMER11, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS),
840 	GATE(SCLK_TIMER10, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS),
841 	GATE(SCLK_TIMER05, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
842 	GATE(SCLK_TIMER04, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
843 	GATE(SCLK_TIMER03, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
844 	GATE(SCLK_TIMER02, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
845 	GATE(SCLK_TIMER01, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
846 	GATE(SCLK_TIMER00, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),