Lines Matching full:xin24m
145 PNAME(mux_pll_p) = { "xin24m" };
148 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
149 PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
150 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
151 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
152 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
156 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
161 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
162 PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
163 PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
164 PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
165 PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
166 PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
176 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
177 PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
178 PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
276 COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
284 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
316 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
323 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
345 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
347 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
353 GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
355 GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
367 GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
372 GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
396 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
409 GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
452 GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
540 GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
571 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
577 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
579 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
581 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
583 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
585 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
587 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
607 SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
612 COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
619 COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
834 GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
881 GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
1041 GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,