Lines Matching full:xin24m
217 PNAME(mux_pll_p) = { "xin24m" };
218 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
230 PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
231 PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
232 PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
233 PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
234 PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
235 PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
236 PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
237 PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
238 PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
239 PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
249 PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" };
255 PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
265 PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
268 PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" };
269 PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" };
271 PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div…
272 PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
274 PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" };
275 PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div…
276 PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" };
277 PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" };
280 PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" };
281 PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" };
285 PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" };
286 PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" };
288 PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" };
289 PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" };
290 PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
291 PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" };
292 PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
293 PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" };
314 PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" };
482 COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
486 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
527 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0,
551 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
581 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
598 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
780 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0,
806 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
826 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
836 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
846 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
868 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
875 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
1066 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
1076 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1194 GATE(CLK_SARADC, "clk_saradc", "xin24m", 0,
1200 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
1378 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
1385 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
1392 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1415 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
1417 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
1419 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
1421 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
1423 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
1425 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
1460 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0,
1481 GATE(CLK_PMU, "clk_pmu", "xin24m", 0,
1491 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
1496 COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED,
1520 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0,
1524 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
1526 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
1531 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0,
1535 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0,
1539 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0,
1543 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0,
1550 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
1557 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0,
1564 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0,
1571 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0,
1579 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,