clk/rockchip/clk-rk3036.c

115 PNAME(mux_pll_p)		= { "xin24m", "xin24m" };
121 PNAME(mux_timer_p)		= { "xin24m", "pclk_peri_src" };
124 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p)   = { "dummy_apll", "dpll", "gpll", "xin24m" };
126 PNAME(mux_mmc_src_p)	= { "apll", "dpll", "gpll", "xin24m" };
130 PNAME(mux_uart0_p)	= { "uart0_src", "uart0_frac", "xin24m" };
131 PNAME(mux_uart1_p)	= { "uart1_src", "uart1_frac", "xin24m" };
132 PNAME(mux_uart2_p)	= { "uart2_src", "uart2_frac", "xin24m" };
177 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
386 	/* xin24m gates */
387 	GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
388 	GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS),
465 	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);  in rk3036_clk_init()