clk/rockchip/clk-px30.c

137 PNAME(mux_pll_p)		= { "xin24m"};
138 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
147 PNAME(mux_gpll_xin24m_p)		= { "gpll", "xin24m"};
149 PNAME(mux_gpll_cpll_npll_xin24m_p)	= { "gpll", "dummy_cpll", "npll", "xin24m" };
150 PNAME(mux_gpll_xin24m_npll_p)		= { "gpll", "xin24m", "npll"};
162 PNAME(mux_uart_src_p)		= { "gpll", "xin24m", "usb480m", "npll" };
168 PNAME(mux_cif_out_p)		= { "xin24m", "dummy_cpll", "npll", "usb480m" };
169 PNAME(mux_dclk_vopb_p)		= { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
170 PNAME(mux_dclk_vopl_p)		= { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
178 PNAME(mux_wifi_pmu_p)		= { "xin24m", "clk_wifi_pmu_src" };
180 PNAME(mux_usbphy_ref_p)		= { "xin24m", "clk_ref24m_pmu" };
181 PNAME(mux_mipidsiphy_ref_p)	= { "xin24m", "clk_ref24m_pmu" };
271 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
301 	GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
360 	GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED,
751 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
753 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
755 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
757 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
759 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
761 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
764 	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
767 	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
770 	COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
777 	GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
919 	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
924 	COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
948 	GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,