clk/rockchip/clk-rk3288.c

192 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
203 PNAME(mux_mmc_src_p)	= { "cpll", "gpll", "xin24m", "xin24m" };
208 PNAME(mux_uart0_p)	= { "uart0_src", "uart0_frac", "xin24m" };
209 PNAME(mux_uart1_p)	= { "uart1_src", "uart1_frac", "xin24m" };
210 PNAME(mux_uart2_p)	= { "uart2_src", "uart2_frac", "xin24m" };
211 PNAME(mux_uart3_p)	= { "uart3_src", "uart3_frac", "xin24m" };
212 PNAME(mux_uart4_p)	= { "uart4_src", "uart4_frac", "xin24m" };
213 PNAME(mux_vip_out_p)	= { "vip_src", "xin24m" };
216 PNAME(mux_edp_24m_p)	= { "ext_edp_24m", "xin24m" };
358 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
394 	GATE(0, "sclk_acc_efuse", "xin24m", 0,
397 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
399 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
401 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
403 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
405 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
407 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
466 	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
558 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
560 	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
562 	GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,
571 	COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
575 	GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
752 	GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
753 	GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
754 	GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
755 	GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
756 	GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),