clk/rockchip/clk-rk3308.c

122 PNAME(mux_pll_p)		= { "xin24m" };
123 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "clk_rtc32k" };
126 PNAME(mux_dpll_vpll0_xin24m_p)	= { "dpll", "vpll0", "xin24m" };
128 PNAME(mux_dpll_vpll0_vpll1_xin24m_p)	= { "dpll", "vpll0", "vpll1", "xin24m" };
129 PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p)	= { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
131 PNAME(mux_vpll0_vpll1_xin24m_p)	= { "vpll0", "vpll1", "xin24m" };
137 PNAME(mux_dclk_vop_p)		= { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
146 PNAME(mux_usbphy_ref_p)		= { "xin24m", "clk_usbphy_ref_src" };
286 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
308 	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
413 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
415 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
417 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
419 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
421 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
423 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
426 	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
429 	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
433 	COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
440 	GATE(SCLK_CPU_BOOST, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
552 	GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
584 	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
605 	GATE(0, "clk_wifi_osc", "xin24m", 0,
614 	GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,