clk/rockchip/clk-rk3228.c

132 PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
137 PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
138 PNAME(mux_hdmiphy_p)		= { "hdmiphy_phy", "xin24m" };
144 PNAME(mux_sclk_hdmi_cec_p)	= { "cpll", "gpll", "xin24m" };
146 PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "xin24m", "usb480m" };
160 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
161 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
162 PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
216 	DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
329 	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
354 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
356 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
358 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
360 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
362 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
364 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
415 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
461 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
463 	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0,
466 	COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,