clk/rockchip/clk-rk3128.c

130 PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
134 PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
142 PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "gpll_div2", "xin24m" };
143 PNAME(mux_clk_cif_out_src_p)		= { "clk_cif_src", "xin24m" };
151 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
152 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
153 PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
156 PNAME(mux_sclk_sfc_src_p)	= { "cpll", "gpll", "gpll_div2", "xin24m" };
205 	DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
291 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
293 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
295 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
297 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
299 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
301 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
304 	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
306 	GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,
308 	GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,
310 	GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,
341 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
390 	COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,