Lines Matching full:xin24m
444 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
445 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
446 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
447 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
449 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
454 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"};
458 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
467 PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" };
468 PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" };
469 PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" };
471 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
472 PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" };
473 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" };
474 PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" };
475 PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
476 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
477 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
478 PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" };
479 PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" };
480 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
481 PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
507 PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
508 PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
509 PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
510 PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
511 PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
512 PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
513 PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
514 PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
515 PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
516 PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
526 PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" };
527 PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" };
528 PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
529 PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "xin32k", "clk_pmu1_100m_src" };
530 PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m…
531 …clk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" };
533 PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" };
534 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
702 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
822 GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0,
834 GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0,
886 GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0,
1020 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
1027 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
1034 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1071 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
1170 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
1172 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
1174 GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
1176 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
1358 GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,
1383 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
1433 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
1452 GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
1470 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
1548 GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0,
1550 GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0,
1552 GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0,
1554 GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0,
1556 GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0,
1558 GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0,
1560 GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0,
1562 GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0,
1572 GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0,
1574 GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0,
1576 GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0,
1595 GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0,
1597 GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0,
1678 GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0,
1680 GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0,
1682 GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0,
1684 GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0,
1949 GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
1956 GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0,
2094 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
2096 GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0,
2144 GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED,
2148 GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED,
2150 GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED,
2153 GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0,
2155 GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0,
2157 GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0,
2202 GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL,
2267 GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0,