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Searched refs:topckgen (Results 1 – 25 of 52) sorted by relevance

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/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8516.dtsi58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
251 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
252 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
Dmt7622.dtsi251 clocks = <&topckgen CLK_TOP_HIF_SEL>;
260 <&topckgen CLK_TOP_AXI_SEL>;
292 topckgen: clock-controller@10210000 { label
293 compatible = "mediatek,mt7622-topckgen";
331 clocks = <&topckgen CLK_TOP_RTC>;
395 clocks = <&topckgen CLK_TOP_UART_SEL>,
406 clocks = <&topckgen CLK_TOP_UART_SEL>,
417 clocks = <&topckgen CLK_TOP_UART_SEL>,
428 clocks = <&topckgen CLK_TOP_UART_SEL>,
439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
Dmt7986a.dtsi156 topckgen: topckgen@1001b000 { label
157 compatible = "mediatek,mt7986-topckgen", "syscon";
202 clocks = <&topckgen CLK_TOP_PWM_SEL>,
242 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
255 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
257 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
258 <&topckgen CLK_TOP_UART_SEL>;
271 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
284 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
308 clocks = <&topckgen CLK_TOP_MPLL_D2>,
[all …]
Dmt2712e.dtsi90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
Dmt8192.dtsi453 topckgen: syscon@10000000 { label
454 compatible = "mediatek,mt8192-topckgen", "syscon";
511 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
529 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
530 <&topckgen CLK_TOP_MFG_REF_SEL>;
572 clocks = <&topckgen CLK_TOP_DISP_SEL>,
586 clocks = <&topckgen CLK_TOP_IPE_SEL>,
599 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
609 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
619 clocks = <&topckgen CLK_TOP_MDP_SEL>,
[all …]
Dmt8188.dtsi904 topckgen: syscon@10000000 { label
905 compatible = "mediatek,mt8188-topckgen", "syscon";
961 clocks = <&topckgen CLK_APMIXED_MFGPLL>,
962 <&topckgen CLK_TOP_MFG_CORE_TMP>;
988 clocks = <&topckgen CLK_TOP_VPP>,
989 <&topckgen CLK_TOP_CAM>,
990 <&topckgen CLK_TOP_CCU>,
991 <&topckgen CLK_TOP_IMG>,
992 <&topckgen CLK_TOP_VENC>,
993 <&topckgen CLK_TOP_VDEC>,
[all …]
Dmt8365.dtsi281 topckgen: syscon@10000000 { label
282 compatible = "mediatek,mt8365-topckgen", "syscon";
318 clocks = <&topckgen CLK_TOP_MM_SEL>,
380 clocks = <&topckgen CLK_TOP_CONN_32K>,
381 <&topckgen CLK_TOP_CONN_26M>;
389 clocks = <&topckgen CLK_TOP_MFG_SEL>;
397 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
407 clocks = <&topckgen CLK_TOP_DSP_SEL>,
408 <&topckgen CLK_TOP_DSP_26M>;
604 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
[all …]
Dmt8186.dtsi848 topckgen: syscon@10000000 { label
849 compatible = "mediatek,mt8186-topckgen", "syscon";
900 clocks = <&topckgen CLK_TOP_MFG>;
927 clocks = <&topckgen CLK_TOP_SENINF>,
928 <&topckgen CLK_TOP_SENINF1>;
936 clocks = <&topckgen CLK_TOP_USB_TOP>,
952 clocks = <&topckgen CLK_TOP_AUDIODSP>,
953 <&topckgen CLK_TOP_ADSP_BUS>;
982 clocks = <&topckgen CLK_TOP_DISP>,
983 <&topckgen CLK_TOP_MDP>,
[all …]
Dmt8173.dtsi349 topckgen: clock-controller@10000000 { label
350 compatible = "mediatek,mt8173-topckgen";
459 clocks = <&topckgen CLK_TOP_MM_SEL>;
465 clocks = <&topckgen CLK_TOP_MM_SEL>,
466 <&topckgen CLK_TOP_VENC_SEL>;
472 clocks = <&topckgen CLK_TOP_MM_SEL>;
478 clocks = <&topckgen CLK_TOP_MM_SEL>;
485 clocks = <&topckgen CLK_TOP_MM_SEL>,
486 <&topckgen CLK_TOP_VENC_LT_SEL>;
534 <&topckgen CLK_TOP_RTC_SEL>;
[all …]
Dmt8167.dtsi20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
51 clocks = <&topckgen CLK_TOP_SMI_MM>;
59 clocks = <&topckgen CLK_TOP_SMI_MM>,
60 <&topckgen CLK_TOP_RG_VDEC>;
67 clocks = <&topckgen CLK_TOP_SMI_MM>;
74 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
75 <&topckgen CLK_TOP_RG_SLOW_MFG>;
Dmt8195.dtsi483 topckgen: syscon@10000000 { label
484 compatible = "mediatek,mt8195-topckgen", "syscon";
544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
580 clocks = <&topckgen CLK_TOP_VPP>,
581 <&topckgen CLK_TOP_CAM>,
582 <&topckgen CLK_TOP_CCU>,
583 <&topckgen CLK_TOP_IMG>,
584 <&topckgen CLK_TOP_VENC>,
585 <&topckgen CLK_TOP_VDEC>,
586 <&topckgen CLK_TOP_WPE_VPP>,
[all …]
Dmt7981b.dtsi66 topckgen: clock-controller@1001b000 { label
67 compatible = "mediatek,mt7981-topckgen", "syscon";
149 clocks = <&topckgen CLK_TOP_CB_M_D2>,
150 <&topckgen CLK_TOP_SPI_SEL>,
163 clocks = <&topckgen CLK_TOP_CB_M_D2>,
164 <&topckgen CLK_TOP_SPI_SEL>,
177 clocks = <&topckgen CLK_TOP_CB_M_D2>,
178 <&topckgen CLK_TOP_SPI_SEL>,
232 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
233 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
Dmt8183.dtsi286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
803 topckgen: syscon@10000000 { label
[all …]
Dmt6795.dtsi269 topckgen: syscon@10000000 { label
270 compatible = "mediatek,mt6795-topckgen", "syscon";
304 clocks = <&topckgen CLK_TOP_MM_SEL>;
310 clocks = <&topckgen CLK_TOP_MM_SEL>,
311 <&topckgen CLK_TOP_VENC_SEL>;
317 clocks = <&topckgen CLK_TOP_MM_SEL>;
324 clocks = <&topckgen CLK_TOP_MM_SEL>;
332 clocks = <&topckgen CLK_TOP_MM_SEL>,
333 <&topckgen CLK_TOP_MJC_SEL>;
403 clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>;
[all …]
Dmt6797.dtsi114 topckgen: topckgen@10000000 { label
115 compatible = "mediatek,mt6797-topckgen";
213 clocks = <&topckgen CLK_TOP_MUX_MFG>,
214 <&topckgen CLK_TOP_MUX_MM>,
215 <&topckgen CLK_TOP_MUX_VDEC>;
Dmt7622-rfb1.dts224 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
225 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
240 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
241 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dmtk-afe-pcm.txt26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
Dmt6797-afe-pcm.txt29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
Dmt8183-afe-pcm.txt32 <&topckgen CLK_TOP_MUX_AUDIO>,
33 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
34 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
/linux-6.12.1/arch/arm/boot/dts/mediatek/
Dmt7629.dtsi98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
137 topckgen: syscon@10210000 { label
138 compatible = "mediatek,mt7629-topckgen", "syscon";
215 clocks = <&topckgen CLK_TOP_UART_SEL>,
226 clocks = <&topckgen CLK_TOP_UART_SEL>,
237 clocks = <&topckgen CLK_TOP_UART_SEL>,
247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
Dmt2701.dtsi126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
343 <&topckgen CLK_TOP_SPI0_SEL>,
389 <&topckgen CLK_TOP_FLASH_SEL>;
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
Dmt7623.dtsi226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
277 clocks = <&topckgen CLK_TOP_MM_SEL>,
278 <&topckgen CLK_TOP_MFG_SEL>,
279 <&topckgen CLK_TOP_ETHIF_SEL>;
423 clocks = <&topckgen CLK_TOP_PWM_SEL>,
487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
488 <&topckgen CLK_TOP_SPI0_SEL>,
552 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
Dmt8135.dtsi127 topckgen: topckgen@10000000 { label
128 compatible = "mediatek,mt8135-topckgen";
/linux-6.12.1/drivers/clk/mediatek/
DMakefile22 clk-mt6795-pericfg.o clk-mt6795-topckgen.o
58 obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
62 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
66 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
78 clk-mt8173-pericfg.o clk-mt8173-topckgen.o
95 obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-apmixedsys.o clk-mt8186-topckgen.o \
108 obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
134 obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \
/linux-6.12.1/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt67 <&topckgen CLK_TOP_MM_SEL>;
68 <&topckgen CLK_TOP_VENC_SEL>,
69 <&topckgen CLK_TOP_VENC_LT_SEL>;

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