dts/mediatek/mt8173.dtsi

349 		topckgen: clock-controller@10000000 {  label
350 			compatible = "mediatek,mt8173-topckgen";
459 					clocks = <&topckgen CLK_TOP_MM_SEL>;
465 					clocks = <&topckgen CLK_TOP_MM_SEL>,
466 						 <&topckgen CLK_TOP_VENC_SEL>;
472 					clocks = <&topckgen CLK_TOP_MM_SEL>;
478 					clocks = <&topckgen CLK_TOP_MM_SEL>;
485 					clocks = <&topckgen CLK_TOP_MM_SEL>,
486 						 <&topckgen CLK_TOP_VENC_LT_SEL>;
534 				 <&topckgen CLK_TOP_RTC_SEL>;
562 			clocks = <&topckgen CLK_TOP_SCP_SEL>;
770 			clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
771 				 <&topckgen CLK_TOP_SPI_SEL>,
794 			assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
797 				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
867 				 <&topckgen CLK_TOP_AUDIO_SEL>,
868 				 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
869 				 <&topckgen CLK_TOP_APLL1_DIV0>,
870 				 <&topckgen CLK_TOP_APLL2_DIV0>,
871 				 <&topckgen CLK_TOP_I2S0_M_SEL>,
872 				 <&topckgen CLK_TOP_I2S1_M_SEL>,
873 				 <&topckgen CLK_TOP_I2S2_M_SEL>,
874 				 <&topckgen CLK_TOP_I2S3_M_SEL>,
875 				 <&topckgen CLK_TOP_I2S3_B_SEL>;
886 			assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
887 					  <&topckgen CLK_TOP_AUD_2_SEL>;
888 			assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
889 						 <&topckgen CLK_TOP_APLL2>;
897 				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
907 				 <&topckgen CLK_TOP_AXI_SEL>;
917 				 <&topckgen CLK_TOP_AXI_SEL>;
927 				 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
942 			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
957 				clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
1000 			assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
1330 			assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1408 				 <&topckgen CLK_TOP_UNIVPLL_D2>,
1409 				 <&topckgen CLK_TOP_CCI400_SEL>,
1410 				 <&topckgen CLK_TOP_VDEC_SEL>,
1411 				 <&topckgen CLK_TOP_VCODECPLL>,
1413 				 <&topckgen CLK_TOP_VENC_LT_SEL>,
1414 				 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1423 			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1424 					  <&topckgen CLK_TOP_CCI400_SEL>,
1425 					  <&topckgen CLK_TOP_VDEC_SEL>,
1428 			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1429 						 <&topckgen CLK_TOP_UNIVPLL_D2>,
1430 						 <&topckgen CLK_TOP_VCODECPLL>;
1476 			clocks = <&topckgen CLK_TOP_VENC_SEL>;
1478 			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1479 			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1526 			clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1528 			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1530 				 <&topckgen CLK_TOP_VCODECPLL_370P5>;