Lines Matching refs:topckgen
251 clocks = <&topckgen CLK_TOP_HIF_SEL>;
260 <&topckgen CLK_TOP_AXI_SEL>;
292 topckgen: clock-controller@10210000 { label
293 compatible = "mediatek,mt7622-topckgen";
331 clocks = <&topckgen CLK_TOP_RTC>;
395 clocks = <&topckgen CLK_TOP_UART_SEL>,
406 clocks = <&topckgen CLK_TOP_UART_SEL>,
417 clocks = <&topckgen CLK_TOP_UART_SEL>,
428 clocks = <&topckgen CLK_TOP_UART_SEL>,
439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
498 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
499 <&topckgen CLK_TOP_SPI0_SEL>,
579 <&topckgen CLK_TOP_FLASH_SEL>;
590 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
591 <&topckgen CLK_TOP_SPI1_SEL>,
604 clocks = <&topckgen CLK_TOP_UART_SEL>,
622 <&topckgen CLK_TOP_AUD1_SEL>,
623 <&topckgen CLK_TOP_AUD2_SEL>,
624 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
625 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
626 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
627 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
628 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
629 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
630 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
631 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
632 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
633 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
634 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
635 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
636 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
637 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
689 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
690 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
691 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
692 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
693 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
694 <&topckgen CLK_TOP_AUD2PLL>;
704 <&topckgen CLK_TOP_MSDC50_0_SEL>;
716 <&topckgen CLK_TOP_AXI_SEL>;
913 clocks = <&topckgen CLK_TOP_ETH_500M>;
970 clocks = <&topckgen CLK_TOP_ETH_SEL>,
979 <&topckgen CLK_TOP_SGMIIPLL>,