Lines Matching refs:topckgen
156 topckgen: topckgen@1001b000 { label
157 compatible = "mediatek,mt7986-topckgen", "syscon";
202 clocks = <&topckgen CLK_TOP_PWM_SEL>,
242 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
255 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
257 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
258 <&topckgen CLK_TOP_UART_SEL>;
271 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
284 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
308 clocks = <&topckgen CLK_TOP_MPLL_D2>,
309 <&topckgen CLK_TOP_SPI_SEL>,
322 clocks = <&topckgen CLK_TOP_MPLL_D2>,
323 <&topckgen CLK_TOP_SPIM_MST_SEL>,
364 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
381 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
382 <&topckgen CLK_TOP_EMMC_250M_SEL>;
384 <&topckgen CLK_TOP_NET1PLL_D5_D2>;
385 clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
468 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
469 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
476 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
483 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
484 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
544 <&topckgen CLK_TOP_NETSYS_SEL>,
545 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
552 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
553 <&topckgen CLK_TOP_SGM_325M_SEL>;
586 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
587 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;