dts/mediatek/mt2712e.dtsi

90 				<&topckgen CLK_TOP_F_MP0_PLL1>;
103 				<&topckgen CLK_TOP_F_MP0_PLL1>;
116 				<&topckgen CLK_TOP_F_BIG_PLL1>;
246 	topckgen: syscon@10000000 {  label
247 		compatible = "mediatek,mt2712-topckgen", "syscon";
285 		clocks = <&topckgen CLK_TOP_MM_SEL>,
286 			 <&topckgen CLK_TOP_MFG_SEL>,
287 			 <&topckgen CLK_TOP_VENC_SEL>,
288 			 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 			 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
290 			 <&topckgen CLK_TOP_VDEC_SEL>;
321 		assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
322 		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
482 		clocks = <&topckgen CLK_TOP_PWM_SEL>,
556 		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
557 			 <&topckgen CLK_TOP_SPI_SEL>,
567 		clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
579 		clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
635 		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
636 			 <&topckgen CLK_TOP_SPI_SEL>,
648 		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
649 			 <&topckgen CLK_TOP_SPI_SEL>,
661 		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
662 			 <&topckgen CLK_TOP_SPI_SEL>,
674 		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
675 			 <&topckgen CLK_TOP_SPI_SEL>,
743 			 <&topckgen CLK_TOP_ETHER_125M_SEL>,
744 			 <&topckgen CLK_TOP_ETHER_50M_SEL>,
745 			 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
746 		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
747 				  <&topckgen CLK_TOP_ETHER_50M_SEL>,
748 				  <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
749 		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
750 					 <&topckgen CLK_TOP_APLL1_D3>,
751 					 <&topckgen CLK_TOP_ETHERPLL_50M>;
780 			 <&topckgen CLK_TOP_AXI_SEL>,
791 			 <&topckgen CLK_TOP_AXI_SEL>,
806 		clocks = <&topckgen CLK_TOP_USB30_SEL>;
821 			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
870 		clocks = <&topckgen CLK_TOP_USB30_SEL>;
885 			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
934 		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
966 		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,