dts/mediatek/mt8183.dtsi

286 			 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
358 				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
381 				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
404 				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
427 				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
450 				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
473 				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
496 				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
803 		topckgen: syscon@10000000 {  label
804 			compatible = "mediatek,mt8183-topckgen", "syscon";
860 					clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
905 					clocks = <&topckgen CLK_TOP_MUX_MM>,
927 						clocks = <&topckgen CLK_TOP_MUX_CAM>,
945 						clocks = <&topckgen CLK_TOP_MUX_IMG>,
968 						clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
969 							 <&topckgen CLK_TOP_MUX_DSP>,
986 							clocks = <&topckgen CLK_TOP_MUX_DSP1>;
994 							clocks = <&topckgen CLK_TOP_MUX_DSP2>;
1021 			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
1177 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1178 				 <&topckgen CLK_TOP_MUX_SPI>,
1217 			clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
1256 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1257 				 <&topckgen CLK_TOP_MUX_SPI>,
1283 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1284 				 <&topckgen CLK_TOP_MUX_SPI>,
1296 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1297 				 <&topckgen CLK_TOP_MUX_SPI>,
1369 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1370 				 <&topckgen CLK_TOP_MUX_SPI>,
1382 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1383 				 <&topckgen CLK_TOP_MUX_SPI>,
1475 					 <&topckgen CLK_TOP_MUX_AUDIO>,
1476 					 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
1477 					 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
1478 					 <&topckgen CLK_TOP_MUX_AUD_1>,
1479 					 <&topckgen CLK_TOP_APLL1_CK>,
1480 					 <&topckgen CLK_TOP_MUX_AUD_2>,
1481 					 <&topckgen CLK_TOP_APLL2_CK>,
1482 					 <&topckgen CLK_TOP_MUX_AUD_ENG1>,
1483 					 <&topckgen CLK_TOP_APLL1_D8>,
1484 					 <&topckgen CLK_TOP_MUX_AUD_ENG2>,
1485 					 <&topckgen CLK_TOP_APLL2_D8>,
1486 					 <&topckgen CLK_TOP_MUX_APLL_I2S0>,
1487 					 <&topckgen CLK_TOP_MUX_APLL_I2S1>,
1488 					 <&topckgen CLK_TOP_MUX_APLL_I2S2>,
1489 					 <&topckgen CLK_TOP_MUX_APLL_I2S3>,
1490 					 <&topckgen CLK_TOP_MUX_APLL_I2S4>,
1491 					 <&topckgen CLK_TOP_MUX_APLL_I2S5>,
1492 					 <&topckgen CLK_TOP_APLL12_DIV0>,
1493 					 <&topckgen CLK_TOP_APLL12_DIV1>,
1494 					 <&topckgen CLK_TOP_APLL12_DIV2>,
1495 					 <&topckgen CLK_TOP_APLL12_DIV3>,
1496 					 <&topckgen CLK_TOP_APLL12_DIV4>,
1497 					 <&topckgen CLK_TOP_APLL12_DIVB>,
1498 					 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
1550 			clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
1562 			clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,