Lines Matching refs:topckgen
453 topckgen: syscon@10000000 { label
454 compatible = "mediatek,mt8192-topckgen", "syscon";
511 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
529 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
530 <&topckgen CLK_TOP_MFG_REF_SEL>;
572 clocks = <&topckgen CLK_TOP_DISP_SEL>,
586 clocks = <&topckgen CLK_TOP_IPE_SEL>,
599 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
609 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
619 clocks = <&topckgen CLK_TOP_MDP_SEL>,
628 clocks = <&topckgen CLK_TOP_VENC_SEL>,
637 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
660 clocks = <&topckgen CLK_TOP_CAM_SEL>,
725 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
726 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
736 <&topckgen CLK_TOP_SPMI_MST_SEL>;
740 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
741 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
794 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
795 <&topckgen CLK_TOP_SPI_SEL>,
829 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
842 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
843 <&topckgen CLK_TOP_SPI_SEL>,
856 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
857 <&topckgen CLK_TOP_SPI_SEL>,
870 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
871 <&topckgen CLK_TOP_SPI_SEL>,
884 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
885 <&topckgen CLK_TOP_SPI_SEL>,
898 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
899 <&topckgen CLK_TOP_SPI_SEL>,
912 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
913 <&topckgen CLK_TOP_SPI_SEL>,
926 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
927 <&topckgen CLK_TOP_SPI_SEL>,
955 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
956 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
957 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
958 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
983 mediatek,topckgen = <&topckgen>;
1007 <&topckgen CLK_TOP_AUDIO_SEL>,
1008 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
1009 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
1010 <&topckgen CLK_TOP_AUD_1_SEL>,
1011 <&topckgen CLK_TOP_APLL1>,
1012 <&topckgen CLK_TOP_AUD_2_SEL>,
1013 <&topckgen CLK_TOP_APLL2>,
1014 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
1015 <&topckgen CLK_TOP_APLL1_D4>,
1016 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
1017 <&topckgen CLK_TOP_APLL2_D4>,
1018 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
1019 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
1020 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
1021 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
1022 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
1023 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
1024 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
1025 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
1026 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
1027 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
1028 <&topckgen CLK_TOP_APLL12_DIV0>,
1029 <&topckgen CLK_TOP_APLL12_DIV1>,
1030 <&topckgen CLK_TOP_APLL12_DIV2>,
1031 <&topckgen CLK_TOP_APLL12_DIV3>,
1032 <&topckgen CLK_TOP_APLL12_DIV4>,
1033 <&topckgen CLK_TOP_APLL12_DIVB>,
1034 <&topckgen CLK_TOP_APLL12_DIV5>,
1035 <&topckgen CLK_TOP_APLL12_DIV6>,
1036 <&topckgen CLK_TOP_APLL12_DIV7>,
1037 <&topckgen CLK_TOP_APLL12_DIV8>,
1038 <&topckgen CLK_TOP_APLL12_DIV9>,
1039 <&topckgen CLK_TOP_AUDIO_H_SEL>,
1115 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
1116 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
1139 clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
1143 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
1396 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
1412 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
1719 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1723 <&topckgen CLK_TOP_MAINPLL_D4>;
1725 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1726 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
1745 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1749 <&topckgen CLK_TOP_MAINPLL_D4>;
1751 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1752 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
1827 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1828 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;