Lines Matching refs:topckgen
483 topckgen: syscon@10000000 { label
484 compatible = "mediatek,mt8195-topckgen", "syscon";
544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
580 clocks = <&topckgen CLK_TOP_VPP>,
581 <&topckgen CLK_TOP_CAM>,
582 <&topckgen CLK_TOP_CCU>,
583 <&topckgen CLK_TOP_IMG>,
584 <&topckgen CLK_TOP_VENC>,
585 <&topckgen CLK_TOP_VDEC>,
586 <&topckgen CLK_TOP_WPE_VPP>,
587 <&topckgen CLK_TOP_CFG_VPP0>,
638 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
655 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
702 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
727 clocks = <&topckgen CLK_TOP_HDMI_APB>;
750 clocks = <&topckgen CLK_TOP_IPE>,
815 clocks = <&topckgen CLK_TOP_SENINF>,
816 <&topckgen CLK_TOP_SENINF2>;
830 clocks = <&topckgen CLK_TOP_ADSP>,
831 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
840 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
841 <&topckgen CLK_TOP_AUD_INTBUS>,
842 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
882 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
893 <&topckgen CLK_TOP_SPMI_M_MST>;
897 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
949 clocks = <&topckgen CLK_TOP_ADSP>,
951 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
952 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
954 <&topckgen CLK_TOP_AUDIO_H>;
984 mediatek,topckgen = <&topckgen>;
992 <&topckgen CLK_TOP_APLL12_DIV0>,
993 <&topckgen CLK_TOP_APLL12_DIV1>,
994 <&topckgen CLK_TOP_APLL12_DIV2>,
995 <&topckgen CLK_TOP_APLL12_DIV3>,
996 <&topckgen CLK_TOP_APLL12_DIV9>,
997 <&topckgen CLK_TOP_A1SYS_HP>,
998 <&topckgen CLK_TOP_AUD_INTBUS>,
999 <&topckgen CLK_TOP_AUDIO_H>,
1000 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1001 <&topckgen CLK_TOP_DPTX_MCK>,
1002 <&topckgen CLK_TOP_I2SO1_MCK>,
1003 <&topckgen CLK_TOP_I2SO2_MCK>,
1004 <&topckgen CLK_TOP_I2SI1_MCK>,
1005 <&topckgen CLK_TOP_I2SI2_MCK>,
1113 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1114 <&topckgen CLK_TOP_SPI>,
1149 clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1160 clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1173 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1174 <&topckgen CLK_TOP_SPI>,
1187 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1188 <&topckgen CLK_TOP_SPI>,
1201 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1202 <&topckgen CLK_TOP_SPI>,
1215 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1216 <&topckgen CLK_TOP_SPI>,
1229 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1230 <&topckgen CLK_TOP_SPI>,
1242 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1253 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1271 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1272 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1273 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1275 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1276 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1277 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1278 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1279 <&topckgen CLK_TOP_ETHPLL_D8>,
1280 <&topckgen CLK_TOP_ETHPLL_D10>;
1359 <&topckgen CLK_TOP_SSUSB_REF>,
1372 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1373 <&topckgen CLK_TOP_SSUSB_XHCI>;
1374 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1375 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1377 <&topckgen CLK_TOP_SSUSB_REF>,
1392 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1405 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1409 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1410 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1420 clocks = <&topckgen CLK_TOP_MSDC30_2>,
1424 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1425 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1448 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1449 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1450 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1451 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1453 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1472 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
1473 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1475 <&topckgen CLK_TOP_SSUSB_P2_REF>,
1488 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1489 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1504 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
1505 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1507 <&topckgen CLK_TOP_SSUSB_P3_REF>,
1520 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1521 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1554 assigned-clocks = <&topckgen CLK_TOP_TL>;
1555 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1607 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1608 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1637 clocks = <&topckgen CLK_TOP_SPINOR>,
1745 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1760 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1928 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1937 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1956 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1965 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
2853 clocks = <&topckgen CLK_TOP_VDEC>,
2856 <&topckgen CLK_TOP_UNIVPLL_D4>;
2858 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2859 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2873 clocks = <&topckgen CLK_TOP_VDEC>,
2876 <&topckgen CLK_TOP_UNIVPLL_D4>;
2878 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2879 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2897 clocks = <&topckgen CLK_TOP_VDEC>,
2900 <&topckgen CLK_TOP_UNIVPLL_D4>;
2902 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2903 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3009 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3010 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3562 <&topckgen CLK_TOP_ETHDR>;