Lines Matching refs:topckgen
98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
137 topckgen: syscon@10210000 { label
138 compatible = "mediatek,mt7629-topckgen", "syscon";
215 clocks = <&topckgen CLK_TOP_UART_SEL>,
226 clocks = <&topckgen CLK_TOP_UART_SEL>,
237 clocks = <&topckgen CLK_TOP_UART_SEL>,
247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
253 <&topckgen CLK_TOP_UNIVPLL2_D4>;
267 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
268 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
281 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
282 <&topckgen CLK_TOP_SPI0_SEL>,
293 <&topckgen CLK_TOP_FLASH_SEL>;
319 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
320 <&topckgen CLK_TOP_SATA_SEL>,
321 <&topckgen CLK_TOP_HIF_SEL>;
322 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
323 <&topckgen CLK_TOP_UNIVPLL2_D4>,
324 <&topckgen CLK_TOP_UNIVPLL1_D2>;
387 assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
388 <&topckgen CLK_TOP_AXI_SEL>,
389 <&topckgen CLK_TOP_HIF_SEL>;
390 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
391 <&topckgen CLK_TOP_SYSPLL1_D2>,
392 <&topckgen CLK_TOP_UNIVPLL1_D2>;
443 clocks = <&topckgen CLK_TOP_ETH_SEL>,
444 <&topckgen CLK_TOP_F10M_REF_SEL>,
466 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
467 <&topckgen CLK_TOP_F10M_REF_SEL>;
468 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
469 <&topckgen CLK_TOP_SGMIIPLL_D2>;