Searched +full:29 +full:- +full:bit (Results 1 – 25 of 1095) sorted by relevance
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| /linux-6.12.1/drivers/media/platform/samsung/exynos4-is/ |
| D | fimc-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
27 #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
30 #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15)
31 #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14)
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| /linux-6.12.1/drivers/media/pci/zoran/ |
| D | zr36057.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * zr36057.h - zr36057 register offsets
14 #define ZR36057_VFEHCR_HS_POL BIT(30)
20 #define ZR36057_VFEVCR_VS_POL BIT(30)
26 #define ZR36057_VFESPFR_EXT_FL BIT(26)
27 #define ZR36057_VFESPFR_TOP_FIELD BIT(25)
28 #define ZR36057_VFESPFR_VCLK_POL BIT(24)
37 #define ZR36057_VFESPFR_ERR_DIF BIT(2)
38 #define ZR36057_VFESPFR_PACK24 BIT(1)
39 #define ZR36057_VFESPFR_LITTLE_ENDIAN BIT(0)
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| /linux-6.12.1/drivers/net/wireless/mediatek/mt76/ |
| D | mt76_connac2_mac.h | 1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
57 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
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| D | mt76_connac3_mac.h | 1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
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| D | mt76x02_dma.h | 1 /* SPDX-License-Identifier: ISC */
13 #define MT_TXD_INFO_NEXT_VLD BIT(16)
14 #define MT_TXD_INFO_TX_BURST BIT(17)
15 #define MT_TXD_INFO_80211 BIT(19)
16 #define MT_TXD_INFO_TSO BIT(20)
17 #define MT_TXD_INFO_CSO BIT(21)
18 #define MT_TXD_INFO_WIV BIT(24)
20 #define MT_TXD_INFO_DPORT GENMASK(29, 27)
24 #define MT_RX_FCE_INFO_SELF_GEN BIT(15)
27 #define MT_RX_FCE_INFO_PCIE_INTR BIT(24)
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| /linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | mac.h | 1 /* SPDX-License-Identifier: ISC */
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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| /linux-6.12.1/drivers/media/platform/samsung/s3c-camif/ |
| D | camif-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include "camif-core.h"
15 #include <media/drv-intf/s3c_camif.h>
19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
24 #define CISRCFMT_ITU601_8BIT BIT(31)
35 #define CIWDOFST_WINOFSEN BIT(31)
36 #define CIWDOFST_CLROVCOFIY BIT(30)
37 #define CIWDOFST_CLROVRLB_PR BIT(28)
38 /* #define CIWDOFST_CLROVPRFIY BIT(27) */
39 #define CIWDOFST_CLROVCOFICB BIT(15)
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| /linux-6.12.1/drivers/usb/dwc2/ |
| D | hw.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hw.h - DesignWare HS OTG Controller hardware definitions
5 * Copyright 2004-2013 Synopsys, Inc.
14 #define GOTGCTL_EUSB2_DISC_SUPP BIT(28)
15 #define GOTGCTL_CHIRPEN BIT(27)
18 #define GOTGCTL_CURMODE_HOST BIT(21)
19 #define GOTGCTL_OTGVER BIT(20)
20 #define GOTGCTL_BSESVLD BIT(19)
21 #define GOTGCTL_ASESVLD BIT(18)
22 #define GOTGCTL_DBNC_SHORT BIT(17)
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| /linux-6.12.1/drivers/mtd/spi-nor/ |
| D | sfdp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
34 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
39 #define BFPT_DWORD1_DTR BIT(19)
40 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
41 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
42 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
45 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
46 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
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| /linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | mac.h | 1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
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| /linux-6.12.1/drivers/net/ipa/reg/ |
| D | ipa_reg-v5.0.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
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| D | ipa_reg-v5.5.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
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| D | ipa_reg-v4.5.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 /* Bit 0 reserved */
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 /* Bit 4 reserved */
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
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| /linux-6.12.1/sound/soc/mediatek/mt8186/ |
| D | mt8186-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
29 #define AHB_IDLE_EN_EXT_SFT 29
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
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| /linux-6.12.1/drivers/net/wireless/realtek/rtw89/ |
| D | txrx.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
77 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
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| D | reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
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| /linux-6.12.1/drivers/media/platform/nxp/dw100/ |
| D | dw100_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define DW100_DEWARP_CTRL_ENABLE BIT(0)
16 #define DW100_DEWARP_CTRL_START BIT(1)
17 #define DW100_DEWARP_CTRL_SOFT_RESET BIT(2)
25 #define DW100_DEWARP_CTRL_SRC_AUTO_SHADOW BIT(8)
26 #define DW100_DEWARP_CTRL_HW_HANDSHAKE BIT(9)
27 #define DW100_DEWARP_CTRL_DST_AUTO_SHADOW BIT(10)
28 #define DW100_DEWARP_CTRL_SPLIT_LINE BIT(11)
37 #define DW100_MAP_LUT_ADDR_ADDR(addr) (((addr) >> 4) & GENMASK(29, 0))
42 #define DW100_IMG_Y_BASE(base) (((base) >> 4) & GENMASK(29, 0))
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| /linux-6.12.1/Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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| /linux-6.12.1/drivers/usb/chipidea/ |
| D | bits.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bits.h - register bits of the ChipIdea USB IP core
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
17 * For 1.x revision, bit24 - bit31 are reserved
18 * For 2.x revision, bit25 - bit28 are 0x2
23 #define CIVERSION (0x7 << 29)
29 #define HCCPARAMS_LEN BIT(17)
33 #define DCCPARAMS_DC BIT(7)
34 #define DCCPARAMS_HC BIT(8)
37 #define TESTMODE_FORCE BIT(0)
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| /linux-6.12.1/drivers/gpu/drm/vc4/ |
| D | vc4_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
67 # define V3D_INT_FRDONE BIT(0)
72 # define V3D_CTRSTA BIT(15)
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| /linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
17 #define XGMAC_CONFIG_SS_OFF 29
18 #define XGMAC_CONFIG_SS_MASK GENMASK(31, 29)
28 #define XGMAC_CONFIG_JD BIT(16)
29 #define XGMAC_CONFIG_TE BIT(0)
32 #define XGMAC_CONFIG_ARPEN BIT(31)
33 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
38 #define XGMAC_CONFIG_S2KP BIT(11)
39 #define XGMAC_CONFIG_LM BIT(10)
40 #define XGMAC_CONFIG_IPC BIT(9)
[all …]
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| /linux-6.12.1/drivers/media/platform/ti/cal/ |
| D | cal_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * LDOs on the device are disabled if CSI-2 module is powered on
25 * Errata does not apply when CSI-2 module is powered off
30 * which is essentially CSI2 REG10 bit 6:
35 #define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
106 #define CAL_HL_HWINFO_NPPI_CTXS0_MASK GENMASK(29, 28)
113 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK BIT(0)
124 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK BIT(0)
128 #define CAL_HL_IRQ_WDMA_END_MASK(m) BIT(m)
129 #define CAL_HL_IRQ_WDMA_START_MASK(m) BIT(m)
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| /linux-6.12.1/drivers/gpu/drm/xe/instructions/ |
| D | xe_gpu_commands.h | 1 /* SPDX-License-Identifier: MIT */
11 #define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
21 #define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
28 #define XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
34 #define PVC_MEM_SET_CMD (2 << 29 | 0x5b << 22)
42 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
44 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */
46 #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29)
50 #define PIPE_CONTROL_LRI_POST_SYNC BIT(23)
54 #define PIPE_CONTROL_TLB_INVALIDATE BIT(18)
|
| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-class-mtd | 3 KernelVersion: 2.6.29
4 Contact: linux-mtd@lists.infradead.org
11 KernelVersion: 2.6.29
12 Contact: linux-mtd@lists.infradead.org
21 KernelVersion: 2.6.29
22 Contact: linux-mtd@lists.infradead.org
24 These directories provide the corresponding read-only device
29 KernelVersion: 2.6.29
30 Contact: linux-mtd@lists.infradead.org
34 read-write device so <minor> will be even.
[all …]
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| /linux-6.12.1/drivers/net/ethernet/emulex/benet/ |
| D | be_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
18 * for the MAILBOX structure. Software must poll the ready bit until this
20 * bits in the address. It must poll the ready bit until the command is
25 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
26 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
40 #define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
[all …]
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