Lines Matching +full:29 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
30 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
31 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
32 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
33 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
34 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
35 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
36 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
37 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
38 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
39 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
40 /* Bit 18 reserved */
41 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
42 [GENQMB_AOOOWR] = BIT(20),
43 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
45 /* Bits 28-29 reserved */
46 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
47 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
53 [CLKON_RX] = BIT(0),
54 [CLKON_PROC] = BIT(1),
55 [TX_WRAPPER] = BIT(2),
56 [CLKON_MISC] = BIT(3),
57 [RAM_ARB] = BIT(4),
58 [FTCH_HPS] = BIT(5),
59 [FTCH_DPS] = BIT(6),
60 [CLKON_HPS] = BIT(7),
61 [CLKON_DPS] = BIT(8),
62 [RX_HPS_CMDQS] = BIT(9),
63 [HPS_DPS_CMDQS] = BIT(10),
64 [DPS_TX_CMDQS] = BIT(11),
65 [RSRC_MNGR] = BIT(12),
66 [CTX_HANDLER] = BIT(13),
67 [ACK_MNGR] = BIT(14),
68 [D_DCPH] = BIT(15),
69 [H_DCPH] = BIT(16),
70 /* Bit 17 reserved */
71 [NTF_TX_CMDQS] = BIT(18),
72 [CLKON_TX_0] = BIT(19),
73 [CLKON_TX_1] = BIT(20),
74 [CLKON_FNR] = BIT(21),
75 [QSB2AXI_CMDQ_L] = BIT(22),
76 [AGGR_WRAPPER] = BIT(23),
77 [RAM_SLAVEWAY] = BIT(24),
78 [CLKON_QMB] = BIT(25),
79 [WEIGHT_ARB] = BIT(26),
80 [GSI_IF] = BIT(27),
81 [CLKON_GLOBAL] = BIT(28),
82 [GLOBAL_2X_CLK] = BIT(29),
83 [DPL_FIFO] = BIT(30),
84 [DRBIP] = BIT(31),
93 [ROUTE_DEF_HDR_TABLE] = BIT(26),
94 [ROUTE_DEF_RETAIN_HDR] = BIT(27),
95 [ROUTE_DIS] = BIT(28),
96 /* Bits 29-31 reserved */
111 /* Bits 8-31 reserved */
119 /* Bits 8-15 reserved */
126 /* Valid bits defined by ipa->available */
131 [ROUTER_CACHE] = BIT(0),
132 /* Bits 1-3 reserved */
133 [FILTER_CACHE] = BIT(4),
134 /* Bits 5-31 reserved */
141 /* Bits 18-31 reserved */
148 /* Bits 0-1 reserved */
151 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
152 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
153 [PA_MASK_EN] = BIT(12),
155 [DUAL_TX_ENABLE] = BIT(17),
156 [SSPND_PA_NO_START_STATE] = BIT(18),
157 /* Bit 19 reserved */
158 [HOLB_STICKY_DROP_EN] = BIT(20),
159 /* Bits 21-31 reserved */
166 [CONST_NON_IDLE_ENABLE] = BIT(16),
167 /* Bits 17-31 reserved */
174 /* Bits 5-6 reserved */
175 [DPL_TIMESTAMP_SEL] = BIT(7),
177 /* Bits 13-15 reserved */
179 /* Bits 21-31 reserved */
186 /* Bits 9-30 reserved */
187 [DIV_ENABLE] = BIT(31),
197 /* Bits 12-31 reserved */
204 /* Bits 6-7 reserved */
206 /* Bits 14-15 reserved */
208 /* Bits 22-23 reserved */
209 [Y_MAX_LIM] = GENMASK(29, 24),
210 /* Bits 30-31 reserved */
218 /* Bits 6-7 reserved */
220 /* Bits 14-15 reserved */
222 /* Bits 22-23 reserved */
223 [Y_MAX_LIM] = GENMASK(29, 24),
224 /* Bits 30-31 reserved */
232 /* Bits 6-7 reserved */
234 /* Bits 14-15 reserved */
236 /* Bits 22-23 reserved */
237 [Y_MAX_LIM] = GENMASK(29, 24),
238 /* Bits 30-31 reserved */
246 /* Bits 6-7 reserved */
248 /* Bits 14-15 reserved */
250 /* Bits 22-23 reserved */
251 [Y_MAX_LIM] = GENMASK(29, 24),
252 /* Bits 30-31 reserved */
260 /* Bits 6-7 reserved */
262 /* Bits 14-15 reserved */
264 /* Bits 22-23 reserved */
265 [Y_MAX_LIM] = GENMASK(29, 24),
266 /* Bits 30-31 reserved */
274 /* Bits 6-7 reserved */
276 /* Bits 14-15 reserved */
278 /* Bits 22-23 reserved */
279 [Y_MAX_LIM] = GENMASK(29, 24),
280 /* Bits 30-31 reserved */
288 /* Bits 6-7 reserved */
290 /* Bits 14-15 reserved */
292 /* Bits 22-23 reserved */
293 [Y_MAX_LIM] = GENMASK(29, 24),
294 /* Bits 30-31 reserved */
302 /* Bits 6-7 reserved */
304 /* Bits 14-15 reserved */
306 /* Bits 22-23 reserved */
307 [Y_MAX_LIM] = GENMASK(29, 24),
308 /* Bits 30-31 reserved */
314 /* Valid bits defined by ipa->available */
319 [FRAG_OFFLOAD_EN] = BIT(0),
322 /* Bit 7 reserved */
323 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
324 /* Bits 9-31 reserved */
331 /* Bits 2-31 reserved */
338 [HDR_OFST_METADATA_VALID] = BIT(6),
341 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
343 /* Bit 26 reserved */
344 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
345 [HDR_LEN_MSB] = GENMASK(29, 28),
352 [HDR_ENDIANNESS] = BIT(0),
353 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
354 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
355 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
358 /* Bits 14-15 reserved */
362 [HDR_BYTES_TO_REMOVE_VALID] = BIT(22),
363 /* Bit 23 reserved */
374 [DCPH_ENABLE] = BIT(3),
377 [PIPE_REPLICATION_EN] = BIT(28),
378 [PAD_EN] = BIT(29),
379 [DRBIP_ACL_ENABLE] = BIT(30),
380 /* Bit 31 reserved */
389 /* Bit 11 reserved */
392 [SW_EOF_ACTIVE] = BIT(23),
393 [FORCE_CLOSE] = BIT(24),
394 /* Bit 25 reserved */
395 [HARD_BYTE_LIMIT_EN] = BIT(26),
396 [AGGR_GRAN_SEL] = BIT(27),
397 /* Bits 28-31 reserved */
403 [HOL_BLOCK_EN] = BIT(0),
404 /* Bits 1-31 reserved */
412 /* Bits 5-7 reserved */
414 /* Bits 10-31 reserved */
422 [SYSPIPE_ERR_DETECTION] = BIT(6),
423 [PACKET_OFFSET_VALID] = BIT(7),
425 [IGNORE_MIN_PKT_ERR] = BIT(14),
426 /* Bit 15 reserved */
434 /* Bits 3-31 reserved */
441 /* Bits 8-31 reserved */
447 [STATUS_EN] = BIT(0),
449 [STATUS_PKT_SUPPRESS] = BIT(9),
450 /* Bits 10-31 reserved */
456 [CACHE_MSK_SRC_ID] = BIT(0),
457 [CACHE_MSK_SRC_IP] = BIT(1),
458 [CACHE_MSK_DST_IP] = BIT(2),
459 [CACHE_MSK_SRC_PORT] = BIT(3),
460 [CACHE_MSK_DST_PORT] = BIT(4),
461 [CACHE_MSK_PROTOCOL] = BIT(5),
462 [CACHE_MSK_METADATA] = BIT(6),
463 /* Bits 7-31 reserved */
470 [CACHE_MSK_SRC_ID] = BIT(0),
471 [CACHE_MSK_SRC_IP] = BIT(1),
472 [CACHE_MSK_DST_IP] = BIT(2),
473 [CACHE_MSK_SRC_PORT] = BIT(3),
474 [CACHE_MSK_DST_PORT] = BIT(4),
475 [CACHE_MSK_PROTOCOL] = BIT(5),
476 [CACHE_MSK_METADATA] = BIT(6),
477 /* Bits 7-31 reserved */
493 [UC_INTR] = BIT(0),
494 /* Bits 1-31 reserved */
499 /* Valid bits defined by ipa->available */
504 /* Valid bits defined by ipa->available */
509 /* Valid bits defined by ipa->available */