Lines Matching +full:29 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 /* Bit 0 reserved */
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 /* Bit 4 reserved */
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
31 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21),
32 /* Bits 22-31 reserved */
38 [CLKON_RX] = BIT(0),
39 [CLKON_PROC] = BIT(1),
40 [TX_WRAPPER] = BIT(2),
41 [CLKON_MISC] = BIT(3),
42 [RAM_ARB] = BIT(4),
43 [FTCH_HPS] = BIT(5),
44 [FTCH_DPS] = BIT(6),
45 [CLKON_HPS] = BIT(7),
46 [CLKON_DPS] = BIT(8),
47 [RX_HPS_CMDQS] = BIT(9),
48 [HPS_DPS_CMDQS] = BIT(10),
49 [DPS_TX_CMDQS] = BIT(11),
50 [RSRC_MNGR] = BIT(12),
51 [CTX_HANDLER] = BIT(13),
52 [ACK_MNGR] = BIT(14),
53 [D_DCPH] = BIT(15),
54 [H_DCPH] = BIT(16),
55 [CLKON_DCMP] = BIT(17),
56 [NTF_TX_CMDQS] = BIT(18),
57 [CLKON_TX_0] = BIT(19),
58 [CLKON_TX_1] = BIT(20),
59 [CLKON_FNR] = BIT(21),
60 [QSB2AXI_CMDQ_L] = BIT(22),
61 [AGGR_WRAPPER] = BIT(23),
62 [RAM_SLAVEWAY] = BIT(24),
63 [CLKON_QMB] = BIT(25),
64 [WEIGHT_ARB] = BIT(26),
65 [GSI_IF] = BIT(27),
66 [CLKON_GLOBAL] = BIT(28),
67 [GLOBAL_2X_CLK] = BIT(29),
68 [DPL_FIFO] = BIT(30),
69 /* Bit 31 reserved */
75 [ROUTE_DIS] = BIT(0),
77 [ROUTE_DEF_HDR_TABLE] = BIT(6),
80 /* Bits 22-23 reserved */
81 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
82 /* Bits 25-31 reserved */
97 /* Bits 8-31 reserved */
105 /* Bits 8-15 reserved */
113 [IPV6_ROUTER_HASH] = BIT(0),
114 /* Bits 1-3 reserved */
115 [IPV6_FILTER_HASH] = BIT(4),
116 /* Bits 5-7 reserved */
117 [IPV4_ROUTER_HASH] = BIT(8),
118 /* Bits 9-11 reserved */
119 [IPV4_FILTER_HASH] = BIT(12),
120 /* Bits 13-31 reserved */
125 /* Valid bits defined by ipa->available */
130 /* Bits 18-31 reserved */
136 /* Valid bits defined by ipa->available */
140 /* Bits 0-1 reserved */
143 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
144 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
145 [PA_MASK_EN] = BIT(12),
147 [DUAL_TX_ENABLE] = BIT(17),
148 /* Bits 18-31 reserved */
155 /* Bits 4-7 reserved */
157 /* Bits 13-15 reserved */
159 /* Bits 21-23 reserved */
161 /* Bits 28-31 reserved */
168 [CONST_NON_IDLE_ENABLE] = BIT(16),
169 /* Bits 17-31 reserved */
176 /* Bits 5-6 reserved */
177 [DPL_TIMESTAMP_SEL] = BIT(7),
179 /* Bits 13-15 reserved */
181 /* Bits 21-31 reserved */
188 /* Bits 9-30 reserved */
189 [DIV_ENABLE] = BIT(31),
204 /* Bits 6-7 reserved */
206 /* Bits 14-15 reserved */
208 /* Bits 22-23 reserved */
209 [Y_MAX_LIM] = GENMASK(29, 24),
210 /* Bits 30-31 reserved */
218 /* Bits 6-7 reserved */
220 /* Bits 14-15 reserved */
222 /* Bits 22-23 reserved */
223 [Y_MAX_LIM] = GENMASK(29, 24),
224 /* Bits 30-31 reserved */
232 /* Bits 6-7 reserved */
234 /* Bits 14-15 reserved */
236 /* Bits 22-23 reserved */
237 [Y_MAX_LIM] = GENMASK(29, 24),
238 /* Bits 30-31 reserved */
246 /* Bits 6-7 reserved */
248 /* Bits 14-15 reserved */
250 /* Bits 22-23 reserved */
251 [Y_MAX_LIM] = GENMASK(29, 24),
252 /* Bits 30-31 reserved */
260 /* Bits 6-7 reserved */
262 /* Bits 14-15 reserved */
264 /* Bits 22-23 reserved */
265 [Y_MAX_LIM] = GENMASK(29, 24),
266 /* Bits 30-31 reserved */
274 /* Bits 6-7 reserved */
276 /* Bits 14-15 reserved */
278 /* Bits 22-23 reserved */
279 [Y_MAX_LIM] = GENMASK(29, 24),
280 /* Bits 30-31 reserved */
287 [FRAG_OFFLOAD_EN] = BIT(0),
290 /* Bit 7 reserved */
291 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
292 /* Bits 9-31 reserved */
299 /* Bits 2-31 reserved */
306 [HDR_OFST_METADATA_VALID] = BIT(6),
309 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
311 [HDR_A5_MUX] = BIT(26),
312 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
313 [HDR_LEN_MSB] = GENMASK(29, 28),
320 [HDR_ENDIANNESS] = BIT(0),
321 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
322 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
323 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
326 /* Bits 14-15 reserved */
330 /* Bits 22-31 reserved */
340 [DCPH_ENABLE] = BIT(3),
342 /* Bits 9-11 reserved */
344 [PIPE_REPLICATION_EN] = BIT(28),
345 [PAD_EN] = BIT(29),
346 /* Bits 30-31 reserved */
355 /* Bit 11 reserved */
358 [SW_EOF_ACTIVE] = BIT(23),
359 [FORCE_CLOSE] = BIT(24),
360 /* Bit 25 reserved */
361 [HARD_BYTE_LIMIT_EN] = BIT(26),
362 [AGGR_GRAN_SEL] = BIT(27),
363 /* Bits 28-31 reserved */
369 [HOL_BLOCK_EN] = BIT(0),
370 /* Bits 1-31 reserved */
378 /* Bits 5-7 reserved */
379 [TIMER_GRAN_SEL] = BIT(8),
380 /* Bits 9-31 reserved */
388 [SYSPIPE_ERR_DETECTION] = BIT(6),
389 [PACKET_OFFSET_VALID] = BIT(7),
391 [IGNORE_MIN_PKT_ERR] = BIT(14),
392 /* Bit 15 reserved */
400 /* Bits 3-31 reserved */
407 /* Bits 8-31 reserved */
413 [STATUS_EN] = BIT(0),
415 /* Bits 6-8 reserved */
416 [STATUS_PKT_SUPPRESS] = BIT(9),
417 /* Bits 10-31 reserved */
423 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
424 [FILTER_HASH_MSK_SRC_IP] = BIT(1),
425 [FILTER_HASH_MSK_DST_IP] = BIT(2),
426 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),
427 [FILTER_HASH_MSK_DST_PORT] = BIT(4),
428 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),
429 [FILTER_HASH_MSK_METADATA] = BIT(6),
431 /* Bits 7-15 reserved */
432 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),
433 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),
434 [ROUTER_HASH_MSK_DST_IP] = BIT(18),
435 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
436 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),
437 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
438 [ROUTER_HASH_MSK_METADATA] = BIT(22),
440 /* Bits 23-31 reserved */
456 [UC_INTR] = BIT(0),
457 /* Bits 1-31 reserved */
462 /* Valid bits defined by ipa->available */
466 /* Valid bits defined by ipa->available */
470 /* Valid bits defined by ipa->available */