Lines Matching +full:29 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hw.h - DesignWare HS OTG Controller hardware definitions
5 * Copyright 2004-2013 Synopsys, Inc.
14 #define GOTGCTL_EUSB2_DISC_SUPP BIT(28)
15 #define GOTGCTL_CHIRPEN BIT(27)
18 #define GOTGCTL_CURMODE_HOST BIT(21)
19 #define GOTGCTL_OTGVER BIT(20)
20 #define GOTGCTL_BSESVLD BIT(19)
21 #define GOTGCTL_ASESVLD BIT(18)
22 #define GOTGCTL_DBNC_SHORT BIT(17)
23 #define GOTGCTL_CONID_B BIT(16)
24 #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
25 #define GOTGCTL_DEVHNPEN BIT(11)
26 #define GOTGCTL_HSTSETHNPEN BIT(10)
27 #define GOTGCTL_HNPREQ BIT(9)
28 #define GOTGCTL_HSTNEGSCS BIT(8)
29 #define GOTGCTL_BVALOVAL BIT(7)
30 #define GOTGCTL_BVALOEN BIT(6)
31 #define GOTGCTL_AVALOVAL BIT(5)
32 #define GOTGCTL_AVALOEN BIT(4)
33 #define GOTGCTL_VBVALOVAL BIT(3)
34 #define GOTGCTL_VBVALOEN BIT(2)
35 #define GOTGCTL_SESREQ BIT(1)
36 #define GOTGCTL_SESREQSCS BIT(0)
39 #define GOTGINT_DBNCE_DONE BIT(19)
40 #define GOTGINT_A_DEV_TOUT_CHG BIT(18)
41 #define GOTGINT_HST_NEG_DET BIT(17)
42 #define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
43 #define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
44 #define GOTGINT_SES_END_DET BIT(2)
47 #define GAHBCFG_AHB_SINGLE BIT(23)
48 #define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
49 #define GAHBCFG_REM_MEM_SUPP BIT(21)
50 #define GAHBCFG_P_TXF_EMP_LVL BIT(8)
51 #define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
52 #define GAHBCFG_DMA_EN BIT(5)
60 #define GAHBCFG_GLBL_INTR_EN BIT(0)
67 #define GUSBCFG_FORCEDEVMODE BIT(30)
68 #define GUSBCFG_FORCEHOSTMODE BIT(29)
69 #define GUSBCFG_TXENDDELAY BIT(28)
70 #define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
71 #define GUSBCFG_ICUSBCAP BIT(26)
72 #define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
73 #define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
74 #define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
75 #define GUSBCFG_TERMSELDLPULSE BIT(22)
76 #define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
77 #define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
78 #define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
79 #define GUSBCFG_ULPI_AUTO_RES BIT(18)
80 #define GUSBCFG_ULPI_FS_LS BIT(17)
81 #define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
82 #define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
85 #define GUSBCFG_HNPCAP BIT(9)
86 #define GUSBCFG_SRPCAP BIT(8)
87 #define GUSBCFG_DDRSEL BIT(7)
88 #define GUSBCFG_PHYSEL BIT(6)
89 #define GUSBCFG_FSINTF BIT(5)
90 #define GUSBCFG_ULPI_UTMI_SEL BIT(4)
91 #define GUSBCFG_PHYIF16 BIT(3)
99 #define GRSTCTL_AHBIDLE BIT(31)
100 #define GRSTCTL_DMAREQ BIT(30)
101 #define GRSTCTL_CSFTRST_DONE BIT(29)
117 #define GRSTCTL_TXFFLSH BIT(5)
118 #define GRSTCTL_RXFFLSH BIT(4)
119 #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
120 #define GRSTCTL_FRMCNTRRST BIT(2)
121 #define GRSTCTL_HSFTRST BIT(1)
122 #define GRSTCTL_CSFTRST BIT(0)
126 #define GINTSTS_WKUPINT BIT(31)
127 #define GINTSTS_SESSREQINT BIT(30)
128 #define GINTSTS_DISCONNINT BIT(29)
129 #define GINTSTS_CONIDSTSCHNG BIT(28)
130 #define GINTSTS_LPMTRANRCVD BIT(27)
131 #define GINTSTS_PTXFEMP BIT(26)
132 #define GINTSTS_HCHINT BIT(25)
133 #define GINTSTS_PRTINT BIT(24)
134 #define GINTSTS_RESETDET BIT(23)
135 #define GINTSTS_FET_SUSP BIT(22)
136 #define GINTSTS_INCOMPL_IP BIT(21)
137 #define GINTSTS_INCOMPL_SOOUT BIT(21)
138 #define GINTSTS_INCOMPL_SOIN BIT(20)
139 #define GINTSTS_OEPINT BIT(19)
140 #define GINTSTS_IEPINT BIT(18)
141 #define GINTSTS_EPMIS BIT(17)
142 #define GINTSTS_RESTOREDONE BIT(16)
143 #define GINTSTS_EOPF BIT(15)
144 #define GINTSTS_ISOUTDROP BIT(14)
145 #define GINTSTS_ENUMDONE BIT(13)
146 #define GINTSTS_USBRST BIT(12)
147 #define GINTSTS_USBSUSP BIT(11)
148 #define GINTSTS_ERLYSUSP BIT(10)
149 #define GINTSTS_I2CINT BIT(9)
150 #define GINTSTS_ULPI_CK_INT BIT(8)
151 #define GINTSTS_GOUTNAKEFF BIT(7)
152 #define GINTSTS_GINNAKEFF BIT(6)
153 #define GINTSTS_NPTXFEMP BIT(5)
154 #define GINTSTS_RXFLVL BIT(4)
155 #define GINTSTS_SOF BIT(3)
156 #define GINTSTS_OTGINT BIT(2)
157 #define GINTSTS_MODEMIS BIT(1)
158 #define GINTSTS_CURMODE_HOST BIT(0)
202 #define GI2CCTL_BSYDNE BIT(31)
203 #define GI2CCTL_RW BIT(30)
204 #define GI2CCTL_I2CDATSE0 BIT(28)
207 #define GI2CCTL_I2CSUSPCTL BIT(25)
208 #define GI2CCTL_ACK BIT(24)
209 #define GI2CCTL_I2CEN BIT(23)
219 #define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16)
220 #define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21)
221 #define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22)
229 #define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
236 #define GHWCFG2_MULTI_PROC_INT BIT(20)
237 #define GHWCFG2_DYNAMIC_FIFO BIT(19)
238 #define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
255 #define GHWCFG2_POINT2POINT BIT(5)
275 #define GHWCFG3_OTG_LPM_EN BIT(15)
276 #define GHWCFG3_BC_SUPPORT BIT(14)
277 #define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
278 #define GHWCFG3_ADP_SUPP BIT(12)
279 #define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
280 #define GHWCFG3_OPTIONAL_FEATURES BIT(10)
281 #define GHWCFG3_VENDOR_CTRL_IF BIT(9)
282 #define GHWCFG3_I2C BIT(8)
283 #define GHWCFG3_OTG_FUNC BIT(7)
290 #define GHWCFG4_DESC_DMA_DYN BIT(31)
291 #define GHWCFG4_DESC_DMA BIT(30)
294 #define GHWCFG4_DED_FIFO_EN BIT(25)
296 #define GHWCFG4_SESSION_END_FILT_EN BIT(24)
297 #define GHWCFG4_B_VALID_FILT_EN BIT(23)
298 #define GHWCFG4_A_VALID_FILT_EN BIT(22)
299 #define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
300 #define GHWCFG4_IDDIG_FILT_EN BIT(20)
308 #define GHWCFG4_ACG_SUPPORTED BIT(12)
309 #define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11)
310 #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10)
311 #define GHWCFG4_XHIBER BIT(7)
312 #define GHWCFG4_HIBER BIT(6)
313 #define GHWCFG4_MIN_AHB_FREQ BIT(5)
314 #define GHWCFG4_POWER_OPTIMIZ BIT(4)
319 #define GLPMCFG_INVSELHSIC BIT(31)
320 #define GLPMCFG_HSICCON BIT(30)
321 #define GLPMCFG_RSTRSLPSTS BIT(29)
322 #define GLPMCFG_ENBESL BIT(28)
325 #define GLPMCFG_SNDLPM BIT(24)
328 #define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21)
329 #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22)
332 #define GLPMCFG_L1RESUMEOK BIT(16)
333 #define GLPMCFG_SLPSTS BIT(15)
339 #define GLPMCFG_ENBLSLPM BIT(7)
340 #define GLPMCFG_BREMOTEWAKE BIT(6)
343 #define GLPMCFG_APPL1RES BIT(1)
344 #define GLPMCFG_LPMCAP BIT(0)
348 #define GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY BIT(29)
351 #define GPWRDN_ADP_INT BIT(23)
352 #define GPWRDN_BSESSVLD BIT(22)
353 #define GPWRDN_IDSTS BIT(21)
356 #define GPWRDN_STS_CHGINT_MSK BIT(18)
357 #define GPWRDN_STS_CHGINT BIT(17)
358 #define GPWRDN_SRP_DET_MSK BIT(16)
359 #define GPWRDN_SRP_DET BIT(15)
360 #define GPWRDN_CONNECT_DET_MSK BIT(14)
361 #define GPWRDN_CONNECT_DET BIT(13)
362 #define GPWRDN_DISCONN_DET_MSK BIT(12)
363 #define GPWRDN_DISCONN_DET BIT(11)
364 #define GPWRDN_RST_DET_MSK BIT(10)
365 #define GPWRDN_RST_DET BIT(9)
366 #define GPWRDN_LNSTSCHG_MSK BIT(8)
367 #define GPWRDN_LNSTSCHG BIT(7)
368 #define GPWRDN_DIS_VBUS BIT(6)
369 #define GPWRDN_PWRDNSWTCH BIT(5)
370 #define GPWRDN_PWRDNRSTN BIT(4)
371 #define GPWRDN_PWRDNCLMP BIT(3)
372 #define GPWRDN_RESTORE BIT(2)
373 #define GPWRDN_PMUACTV BIT(1)
374 #define GPWRDN_PMUINTSEL BIT(0)
385 #define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
386 #define ADPCTL_ADP_SNS_INT_MSK BIT(25)
387 #define ADPCTL_ADP_PRB_INT_MSK BIT(24)
388 #define ADPCTL_ADP_TMOUT_INT BIT(23)
389 #define ADPCTL_ADP_SNS_INT BIT(22)
390 #define ADPCTL_ADP_PRB_INT BIT(21)
391 #define ADPCTL_ADPENA BIT(20)
392 #define ADPCTL_ADPRES BIT(19)
393 #define ADPCTL_ENASNS BIT(18)
394 #define ADPCTL_ENAPRB BIT(17)
407 #define GREFCLK_REF_CLK_MODE BIT(14)
412 #define GINTMSK2_WKUP_ALERT_INT_MSK BIT(0)
415 #define GINTSTS2_WKUP_ALERT_INT BIT(0)
420 #define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
433 #define DCFG_DESCDMA_EN BIT(23)
438 #define DCFG_IPG_ISOC_SUPPORDED BIT(17)
447 #define DCFG_NZ_STS_OUT_HSHK BIT(2)
456 #define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
457 #define DCTL_PWRONPRGDONE BIT(11)
458 #define DCTL_CGOUTNAK BIT(10)
459 #define DCTL_SGOUTNAK BIT(9)
460 #define DCTL_CGNPINNAK BIT(8)
461 #define DCTL_SGNPINNAK BIT(7)
464 #define DCTL_GOUTNAKSTS BIT(3)
465 #define DCTL_GNPINNAKSTS BIT(2)
466 #define DCTL_SFTDISCON BIT(1)
467 #define DCTL_RMTWKUPSIG BIT(0)
474 #define DSTS_ERRATICERR BIT(3)
481 #define DSTS_SUSPSTS BIT(0)
484 #define DIEPMSK_NAKMSK BIT(13)
485 #define DIEPMSK_BNAININTRMSK BIT(9)
486 #define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
487 #define DIEPMSK_TXFIFOEMPTY BIT(7)
488 #define DIEPMSK_INEPNAKEFFMSK BIT(6)
489 #define DIEPMSK_INTKNEPMISMSK BIT(5)
490 #define DIEPMSK_INTKNTXFEMPMSK BIT(4)
491 #define DIEPMSK_TIMEOUTMSK BIT(3)
492 #define DIEPMSK_AHBERRMSK BIT(2)
493 #define DIEPMSK_EPDISBLDMSK BIT(1)
494 #define DIEPMSK_XFERCOMPLMSK BIT(0)
497 #define DOEPMSK_BNAMSK BIT(9)
498 #define DOEPMSK_BACK2BACKSETUP BIT(6)
499 #define DOEPMSK_STSPHSERCVDMSK BIT(5)
500 #define DOEPMSK_OUTTKNEPDISMSK BIT(4)
501 #define DOEPMSK_SETUPMSK BIT(3)
502 #define DOEPMSK_AHBERRMSK BIT(2)
503 #define DOEPMSK_EPDISBLDMSK BIT(1)
504 #define DOEPMSK_XFERCOMPLMSK BIT(0)
528 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
529 * bits[25..22] - should always be zero, this isn't a periodic endpoint
530 * bits[10..0] - MPS setting different for EP0
539 #define DXEPCTL_EPENA BIT(31)
540 #define DXEPCTL_EPDIS BIT(30)
541 #define DXEPCTL_SETD1PID BIT(29)
542 #define DXEPCTL_SETODDFR BIT(29)
543 #define DXEPCTL_SETD0PID BIT(28)
544 #define DXEPCTL_SETEVENFR BIT(28)
545 #define DXEPCTL_SNAK BIT(27)
546 #define DXEPCTL_CNAK BIT(26)
551 #define DXEPCTL_STALL BIT(21)
552 #define DXEPCTL_SNP BIT(20)
559 #define DXEPCTL_NAKSTS BIT(17)
560 #define DXEPCTL_DPID BIT(16)
561 #define DXEPCTL_EOFRNUM BIT(16)
562 #define DXEPCTL_USBACTEP BIT(15)
574 #define DXEPINT_SETUP_RCVD BIT(15)
575 #define DXEPINT_NYETINTRPT BIT(14)
576 #define DXEPINT_NAKINTRPT BIT(13)
577 #define DXEPINT_BBLEERRINTRPT BIT(12)
578 #define DXEPINT_PKTDRPSTS BIT(11)
579 #define DXEPINT_BNAINTR BIT(9)
580 #define DXEPINT_TXFIFOUNDRN BIT(8)
581 #define DXEPINT_OUTPKTERR BIT(8)
582 #define DXEPINT_TXFEMP BIT(7)
583 #define DXEPINT_INEPNAKEFF BIT(6)
584 #define DXEPINT_BACK2BACKSETUP BIT(6)
585 #define DXEPINT_INTKNEPMIS BIT(5)
586 #define DXEPINT_STSPHSERCVD BIT(5)
587 #define DXEPINT_INTKNTXFEMP BIT(4)
588 #define DXEPINT_OUTTKNEPDIS BIT(4)
589 #define DXEPINT_TIMEOUT BIT(3)
590 #define DXEPINT_SETUP BIT(3)
591 #define DXEPINT_AHBERR BIT(2)
592 #define DXEPINT_EPDISBLD BIT(1)
593 #define DXEPINT_XFERCOMPL BIT(0)
606 #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
607 #define DOEPTSIZ0_SUPCNT_SHIFT 29
609 #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
610 #define DOEPTSIZ0_PKTCNT BIT(19)
616 #define DXEPTSIZ_MC_MASK (0x3 << 29)
617 #define DXEPTSIZ_MC_SHIFT 29
619 #define DXEPTSIZ_MC(_x) ((_x) << 29)
637 #define PCGCTL_IF_DEV_MODE BIT(31)
638 #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
639 #define PCGCTL_P2HD_PRT_SPD_SHIFT 29
644 #define PCGCTL_MAX_TERMSEL BIT(19)
647 #define PCGCTL_PORT_POWER BIT(16)
650 #define PCGCTL_ESS_REG_RESTORED BIT(13)
651 #define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
652 #define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
653 #define PCGCTL_ENBL_EXTND_HIBER BIT(10)
654 #define PCGCTL_RESTOREMODE BIT(9)
655 #define PCGCTL_RESETAFTSUSP BIT(8)
656 #define PCGCTL_DEEP_SLEEP BIT(7)
657 #define PCGCTL_PHY_IN_SLEEP BIT(6)
658 #define PCGCTL_ENBL_SLEEP_GATING BIT(5)
659 #define PCGCTL_RSTPDWNMODULE BIT(3)
660 #define PCGCTL_PWRCLMP BIT(2)
661 #define PCGCTL_GATEHCLK BIT(1)
662 #define PCGCTL_STOPPCLK BIT(0)
666 #define PCGCCTL1_GATEEN BIT(0)
673 #define HCFG_MODECHTIMEN BIT(31)
674 #define HCFG_PERSCHEDENA BIT(26)
679 #define HCFG_FRLISTEN_16 BIT(24)
685 #define HCFG_DESCDMA BIT(23)
688 #define HCFG_ENA32KHZ BIT(7)
689 #define HCFG_FSLSSUPP BIT(2)
699 #define HFIR_RLDCTRL BIT(16)
709 #define TXSTS_QTOP_ODD BIT(31)
714 #define TXSTS_QTOP_TERMINATE BIT(24)
732 #define HPRT0_PWR BIT(12)
735 #define HPRT0_RST BIT(8)
736 #define HPRT0_SUSP BIT(7)
737 #define HPRT0_RES BIT(6)
738 #define HPRT0_OVRCURRCHG BIT(5)
739 #define HPRT0_OVRCURRACT BIT(4)
740 #define HPRT0_ENACHG BIT(3)
741 #define HPRT0_ENA BIT(2)
742 #define HPRT0_CONNDET BIT(1)
743 #define HPRT0_CONNSTS BIT(0)
746 #define HCCHAR_CHENA BIT(31)
747 #define HCCHAR_CHDIS BIT(30)
748 #define HCCHAR_ODDFRM BIT(29)
755 #define HCCHAR_LSPDDEV BIT(17)
756 #define HCCHAR_EPDIR BIT(15)
763 #define HCSPLT_SPLTENA BIT(31)
764 #define HCSPLT_COMPSPLT BIT(16)
779 #define HCINTMSK_FRM_LIST_ROLL BIT(13)
780 #define HCINTMSK_XCS_XACT BIT(12)
781 #define HCINTMSK_BNA BIT(11)
782 #define HCINTMSK_DATATGLERR BIT(10)
783 #define HCINTMSK_FRMOVRUN BIT(9)
784 #define HCINTMSK_BBLERR BIT(8)
785 #define HCINTMSK_XACTERR BIT(7)
786 #define HCINTMSK_NYET BIT(6)
787 #define HCINTMSK_ACK BIT(5)
788 #define HCINTMSK_NAK BIT(4)
789 #define HCINTMSK_STALL BIT(3)
790 #define HCINTMSK_AHBERR BIT(2)
791 #define HCINTMSK_CHHLTD BIT(1)
792 #define HCINTMSK_XFERCOMPL BIT(0)
795 #define TSIZ_DOPNG BIT(31)
796 #define TSIZ_SC_MC_PID_MASK (0x3 << 29)
797 #define TSIZ_SC_MC_PID_SHIFT 29
819 * struct dwc2_dma_desc - DMA descriptor structure,
835 #define HOST_DMA_A BIT(31)
838 #define HOST_DMA_STS_PKTERR BIT(28)
839 #define HOST_DMA_EOL BIT(26)
840 #define HOST_DMA_IOC BIT(25)
841 #define HOST_DMA_SUP BIT(24)
842 #define HOST_DMA_ALT_QTD BIT(23)
864 #define DEV_DMA_L BIT(27)
865 #define DEV_DMA_SHORT BIT(26)
866 #define DEV_DMA_IOC BIT(25)
867 #define DEV_DMA_SR BIT(24)
868 #define DEV_DMA_MTRF BIT(23)