Lines Matching +full:29 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
30 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
31 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
32 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
33 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
34 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
35 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
36 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
37 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
38 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
39 /* Bits 17-18 reserved */
40 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
41 [GENQMB_AOOOWR] = BIT(20),
42 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
44 /* Bits 28-29 reserved */
45 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
46 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
52 [CLKON_RX] = BIT(0),
53 [CLKON_PROC] = BIT(1),
54 [TX_WRAPPER] = BIT(2),
55 [CLKON_MISC] = BIT(3),
56 [RAM_ARB] = BIT(4),
57 [FTCH_HPS] = BIT(5),
58 [FTCH_DPS] = BIT(6),
59 [CLKON_HPS] = BIT(7),
60 [CLKON_DPS] = BIT(8),
61 [RX_HPS_CMDQS] = BIT(9),
62 [HPS_DPS_CMDQS] = BIT(10),
63 [DPS_TX_CMDQS] = BIT(11),
64 [RSRC_MNGR] = BIT(12),
65 [CTX_HANDLER] = BIT(13),
66 [ACK_MNGR] = BIT(14),
67 [D_DCPH] = BIT(15),
68 [H_DCPH] = BIT(16),
69 /* Bit 17 reserved */
70 [NTF_TX_CMDQS] = BIT(18),
71 [CLKON_TX_0] = BIT(19),
72 [CLKON_TX_1] = BIT(20),
73 [CLKON_FNR] = BIT(21),
74 [QSB2AXI_CMDQ_L] = BIT(22),
75 [AGGR_WRAPPER] = BIT(23),
76 [RAM_SLAVEWAY] = BIT(24),
77 [CLKON_QMB] = BIT(25),
78 [WEIGHT_ARB] = BIT(26),
79 [GSI_IF] = BIT(27),
80 [CLKON_GLOBAL] = BIT(28),
81 [GLOBAL_2X_CLK] = BIT(29),
82 [DPL_FIFO] = BIT(30),
83 [DRBIP] = BIT(31),
92 [ROUTE_DEF_HDR_TABLE] = BIT(26),
93 [ROUTE_DEF_RETAIN_HDR] = BIT(27),
94 [ROUTE_DIS] = BIT(28),
95 /* Bits 29-31 reserved */
110 /* Bits 8-31 reserved */
118 /* Bits 8-15 reserved */
125 /* Valid bits defined by ipa->available */
130 [ROUTER_CACHE] = BIT(0),
131 /* Bits 1-3 reserved */
132 [FILTER_CACHE] = BIT(4),
133 /* Bits 5-31 reserved */
140 /* Bits 18-31 reserved */
147 /* Bits 0-1 reserved */
150 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
151 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
152 [PA_MASK_EN] = BIT(12),
154 [DUAL_TX_ENABLE] = BIT(17),
155 [SSPND_PA_NO_START_STATE] = BIT(18),
156 /* Bit 19 reserved */
157 [HOLB_STICKY_DROP_EN] = BIT(20),
158 /* Bits 21-31 reserved */
165 [CONST_NON_IDLE_ENABLE] = BIT(16),
166 /* Bits 17-31 reserved */
172 /* Bits 0-7 reserved */
174 /* Bits 13-15 reserved */
176 /* Bits 21-31 reserved */
183 /* Bits 9-30 reserved */
184 [DIV_ENABLE] = BIT(31),
194 /* Bits 12-31 reserved */
201 /* Bits 6-7 reserved */
203 /* Bits 14-15 reserved */
205 /* Bits 22-23 reserved */
206 [Y_MAX_LIM] = GENMASK(29, 24),
207 /* Bits 30-31 reserved */
215 /* Bits 6-7 reserved */
217 /* Bits 14-15 reserved */
219 /* Bits 22-23 reserved */
220 [Y_MAX_LIM] = GENMASK(29, 24),
221 /* Bits 30-31 reserved */
229 /* Bits 6-7 reserved */
231 /* Bits 14-15 reserved */
233 /* Bits 22-23 reserved */
234 [Y_MAX_LIM] = GENMASK(29, 24),
235 /* Bits 30-31 reserved */
243 /* Bits 6-7 reserved */
245 /* Bits 14-15 reserved */
247 /* Bits 22-23 reserved */
248 [Y_MAX_LIM] = GENMASK(29, 24),
249 /* Bits 30-31 reserved */
257 /* Bits 6-7 reserved */
259 /* Bits 14-15 reserved */
261 /* Bits 22-23 reserved */
262 [Y_MAX_LIM] = GENMASK(29, 24),
263 /* Bits 30-31 reserved */
271 /* Bits 6-7 reserved */
273 /* Bits 14-15 reserved */
275 /* Bits 22-23 reserved */
276 [Y_MAX_LIM] = GENMASK(29, 24),
277 /* Bits 30-31 reserved */
285 /* Bits 6-7 reserved */
287 /* Bits 14-15 reserved */
289 /* Bits 22-23 reserved */
290 [Y_MAX_LIM] = GENMASK(29, 24),
291 /* Bits 30-31 reserved */
299 /* Bits 6-7 reserved */
301 /* Bits 14-15 reserved */
303 /* Bits 22-23 reserved */
304 [Y_MAX_LIM] = GENMASK(29, 24),
305 /* Bits 30-31 reserved */
311 /* Valid bits defined by ipa->available */
316 [FRAG_OFFLOAD_EN] = BIT(0),
319 /* Bit 7 reserved */
320 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
321 [PIPE_REPLICATE_EN] = BIT(9),
322 /* Bits 10-31 reserved */
329 /* Bits 2-31 reserved */
336 [HDR_OFST_METADATA_VALID] = BIT(6),
339 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
341 /* Bit 26 reserved */
342 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
343 [HDR_LEN_MSB] = GENMASK(29, 28),
350 [HDR_ENDIANNESS] = BIT(0),
351 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
352 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
353 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
356 /* Bits 14-15 reserved */
360 [HDR_BYTES_TO_REMOVE_VALID] = BIT(22),
361 /* Bit 23 reserved */
372 [DCPH_ENABLE] = BIT(3),
375 /* Bit 28 reserved */
376 [PAD_EN] = BIT(29),
377 [DRBIP_ACL_ENABLE] = BIT(30),
378 /* Bit 31 reserved */
387 /* Bit 11 reserved */
390 [SW_EOF_ACTIVE] = BIT(23),
391 [FORCE_CLOSE] = BIT(24),
392 /* Bit 25 reserved */
393 [HARD_BYTE_LIMIT_EN] = BIT(26),
394 [AGGR_GRAN_SEL] = BIT(27),
395 [AGGR_COAL_L2] = BIT(28),
396 /* Bits 27-31 reserved */
402 [HOL_BLOCK_EN] = BIT(0),
403 /* Bits 1-31 reserved */
411 /* Bits 5-7 reserved */
413 /* Bits 10-31 reserved */
421 [SYSPIPE_ERR_DETECTION] = BIT(6),
422 [PACKET_OFFSET_VALID] = BIT(7),
424 [IGNORE_MIN_PKT_ERR] = BIT(14),
425 /* Bit 15 reserved */
433 /* Bits 3-31 reserved */
440 /* Bits 8-31 reserved */
446 [STATUS_EN] = BIT(0),
448 [STATUS_PKT_SUPPRESS] = BIT(9),
449 /* Bits 10-31 reserved */
455 [CACHE_MSK_SRC_ID] = BIT(0),
456 [CACHE_MSK_SRC_IP] = BIT(1),
457 [CACHE_MSK_DST_IP] = BIT(2),
458 [CACHE_MSK_SRC_PORT] = BIT(3),
459 [CACHE_MSK_DST_PORT] = BIT(4),
460 [CACHE_MSK_PROTOCOL] = BIT(5),
461 [CACHE_MSK_METADATA] = BIT(6),
462 /* Bits 7-31 reserved */
469 [CACHE_MSK_SRC_ID] = BIT(0),
470 [CACHE_MSK_SRC_IP] = BIT(1),
471 [CACHE_MSK_DST_IP] = BIT(2),
472 [CACHE_MSK_SRC_PORT] = BIT(3),
473 [CACHE_MSK_DST_PORT] = BIT(4),
474 [CACHE_MSK_PROTOCOL] = BIT(5),
475 [CACHE_MSK_METADATA] = BIT(6),
476 /* Bits 7-31 reserved */
492 [UC_INTR] = BIT(0),
493 /* Bits 1-31 reserved */
498 /* Valid bits defined by ipa->available */
503 /* Valid bits defined by ipa->available */
508 /* Valid bits defined by ipa->available */