Lines Matching +full:29 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
27 #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
30 #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15)
31 #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14)
36 #define FIMC_REG_CIGCTRL_SWRST BIT(31)
37 #define FIMC_REG_CIGCTRL_CAMRST_A BIT(30)
38 #define FIMC_REG_CIGCTRL_SELCAM_ITU_A BIT(29)
45 #define FIMC_REG_CIGCTRL_INVPOLPCLK BIT(26)
46 #define FIMC_REG_CIGCTRL_INVPOLVSYNC BIT(25)
47 #define FIMC_REG_CIGCTRL_INVPOLHREF BIT(24)
48 #define FIMC_REG_CIGCTRL_IRQ_OVFEN BIT(22)
49 #define FIMC_REG_CIGCTRL_HREF_MASK BIT(21)
50 #define FIMC_REG_CIGCTRL_IRQ_LEVEL BIT(20)
51 #define FIMC_REG_CIGCTRL_IRQ_CLR BIT(19)
52 #define FIMC_REG_CIGCTRL_IRQ_ENABLE BIT(16)
53 #define FIMC_REG_CIGCTRL_SHDW_DISABLE BIT(12)
54 /* 0 - selects Writeback A (LCD), 1 - selects Writeback B (LCD/ISP) */
55 #define FIMC_REG_CIGCTRL_SELWB_A BIT(10)
56 #define FIMC_REG_CIGCTRL_CAM_JPEG BIT(8)
57 #define FIMC_REG_CIGCTRL_SELCAM_MIPI_A BIT(7)
58 #define FIMC_REG_CIGCTRL_CAMIF_SELWB BIT(6)
59 /* 0 - ITU601; 1 - ITU709 */
60 #define FIMC_REG_CIGCTRL_CSC_ITU601_709 BIT(5)
61 #define FIMC_REG_CIGCTRL_INVPOLHSYNC BIT(4)
62 #define FIMC_REG_CIGCTRL_SELCAM_MIPI BIT(3)
63 #define FIMC_REG_CIGCTRL_INVPOLFIELD BIT(1)
64 #define FIMC_REG_CIGCTRL_INTERLACE BIT(0)
78 #define FIMC_REG_CITRGFMT_INROT90 BIT(31)
79 #define FIMC_REG_CITRGFMT_YCBCR420 (0 << 29)
80 #define FIMC_REG_CITRGFMT_YCBCR422 (1 << 29)
81 #define FIMC_REG_CITRGFMT_YCBCR422_1P (2 << 29)
82 #define FIMC_REG_CITRGFMT_RGB (3 << 29)
83 #define FIMC_REG_CITRGFMT_FMT_MASK (3 << 29)
91 #define FIMC_REG_CITRGFMT_OUTROT90 BIT(13)
101 #define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE BIT(2)
114 /* Pre-scaler control 1 */
121 #define FIMC_REG_CISCCTRL_SCALERBYPASS BIT(31)
122 #define FIMC_REG_CISCCTRL_SCALEUP_H BIT(30)
123 #define FIMC_REG_CISCCTRL_SCALEUP_V BIT(29)
124 #define FIMC_REG_CISCCTRL_CSCR2Y_WIDE BIT(28)
125 #define FIMC_REG_CISCCTRL_CSCY2R_WIDE BIT(27)
126 #define FIMC_REG_CISCCTRL_LCDPATHEN_FIFO BIT(26)
127 #define FIMC_REG_CISCCTRL_INTERLACE BIT(25)
128 #define FIMC_REG_CISCCTRL_SCALERSTART BIT(15)
137 #define FIMC_REG_CISCCTRL_RGB_EXT BIT(10)
138 #define FIMC_REG_CISCCTRL_ONE2ONE BIT(9)
152 #define FIMC_REG_CISTATUS_OVFIY BIT(31)
153 #define FIMC_REG_CISTATUS_OVFICB BIT(30)
154 #define FIMC_REG_CISTATUS_OVFICR BIT(29)
155 #define FIMC_REG_CISTATUS_VSYNC BIT(28)
158 #define FIMC_REG_CISTATUS_WINOFF_EN BIT(25)
159 #define FIMC_REG_CISTATUS_IMGCPT_EN BIT(22)
160 #define FIMC_REG_CISTATUS_IMGCPT_SCEN BIT(21)
161 #define FIMC_REG_CISTATUS_VSYNC_A BIT(20)
162 #define FIMC_REG_CISTATUS_VSYNC_B BIT(19)
163 #define FIMC_REG_CISTATUS_OVRLB BIT(18)
164 #define FIMC_REG_CISTATUS_FRAME_END BIT(17)
165 #define FIMC_REG_CISTATUS_LASTCAPT_END BIT(16)
166 #define FIMC_REG_CISTATUS_VVALID_A BIT(15)
167 #define FIMC_REG_CISTATUS_VVALID_B BIT(14)
174 #define FIMC_REG_CIIMGCPT_IMGCPTEN BIT(31)
175 #define FIMC_REG_CIIMGCPT_IMGCPTEN_SC BIT(30)
176 #define FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE BIT(25)
177 #define FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT BIT(18)
184 #define FIMC_REG_CIIMGEFF_IE_ENABLE BIT(30)
185 #define FIMC_REG_CIIMGEFF_IE_SC_BEFORE (0 << 29)
186 #define FIMC_REG_CIIMGEFF_IE_SC_AFTER (1 << 29)
203 #define FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN BIT(31)
204 #define FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS BIT(30)
220 #define FIMC_REG_MSCTRL_FIFO_CTRL_FULL BIT(12)
228 #define FIMC_REG_MSCTRL_INPUT_MEMORY BIT(3)
229 #define FIMC_REG_MSCTRL_INPUT_MASK BIT(3)
235 #define FIMC_REG_MSCTRL_ENVID BIT(0)
262 #define FIMC_REG_CIDMAPARAM_R_LINEAR (0 << 29)
263 #define FIMC_REG_CIDMAPARAM_R_64X32 (3 << 29)
266 #define FIMC_REG_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13))
275 #define FIMC_REG_CSIIMGFMT_USER(x) (0x30 + x - 1)
282 #define SYSREG_ISPBLK_FIFORST_CAM_BLK BIT(7)
285 #define SYSREG_CAMBLK_FIFORST_ISP BIT(15)
326 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
335 writel(mask, dev->regs + FIMC_REG_CIFCNTSEQ); in fimc_hw_set_dma_seq()