1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2023-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/bits.h> 7 #include <linux/types.h> 8 9 #include "../ipa_reg.h" 10 #include "../ipa_version.h" 11 12 static const u32 reg_flavor_0_fmask[] = { 13 [MAX_PIPES] = GENMASK(7, 0), 14 [MAX_CONS_PIPES] = GENMASK(15, 8), 15 [MAX_PROD_PIPES] = GENMASK(23, 16), 16 [PROD_LOWEST] = GENMASK(31, 24), 17 }; 18 19 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000); 20 21 static const u32 reg_comp_cfg_fmask[] = { 22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 23 [GSI_SNOC_BYPASS_DIS] = BIT(1), 24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 26 /* Bit 4 reserved */ 27 [IPA_QMB_SELECT_CONS_EN] = BIT(5), 28 [IPA_QMB_SELECT_PROD_EN] = BIT(6), 29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 30 [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 31 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 32 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 33 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 34 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 35 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 36 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 37 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 38 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 39 /* Bits 17-18 reserved */ 40 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19), 41 [GENQMB_AOOOWR] = BIT(20), 42 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21), 43 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22), 44 /* Bits 28-29 reserved */ 45 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30), 46 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31), 47 }; 48 49 REG_FIELDS(COMP_CFG, comp_cfg, 0x00000048); 50 51 static const u32 reg_clkon_cfg_fmask[] = { 52 [CLKON_RX] = BIT(0), 53 [CLKON_PROC] = BIT(1), 54 [TX_WRAPPER] = BIT(2), 55 [CLKON_MISC] = BIT(3), 56 [RAM_ARB] = BIT(4), 57 [FTCH_HPS] = BIT(5), 58 [FTCH_DPS] = BIT(6), 59 [CLKON_HPS] = BIT(7), 60 [CLKON_DPS] = BIT(8), 61 [RX_HPS_CMDQS] = BIT(9), 62 [HPS_DPS_CMDQS] = BIT(10), 63 [DPS_TX_CMDQS] = BIT(11), 64 [RSRC_MNGR] = BIT(12), 65 [CTX_HANDLER] = BIT(13), 66 [ACK_MNGR] = BIT(14), 67 [D_DCPH] = BIT(15), 68 [H_DCPH] = BIT(16), 69 /* Bit 17 reserved */ 70 [NTF_TX_CMDQS] = BIT(18), 71 [CLKON_TX_0] = BIT(19), 72 [CLKON_TX_1] = BIT(20), 73 [CLKON_FNR] = BIT(21), 74 [QSB2AXI_CMDQ_L] = BIT(22), 75 [AGGR_WRAPPER] = BIT(23), 76 [RAM_SLAVEWAY] = BIT(24), 77 [CLKON_QMB] = BIT(25), 78 [WEIGHT_ARB] = BIT(26), 79 [GSI_IF] = BIT(27), 80 [CLKON_GLOBAL] = BIT(28), 81 [GLOBAL_2X_CLK] = BIT(29), 82 [DPL_FIFO] = BIT(30), 83 [DRBIP] = BIT(31), 84 }; 85 86 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000050); 87 88 static const u32 reg_route_fmask[] = { 89 [ROUTE_DEF_PIPE] = GENMASK(7, 0), 90 [ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8), 91 [ROUTE_DEF_HDR_OFST] = GENMASK(25, 16), 92 [ROUTE_DEF_HDR_TABLE] = BIT(26), 93 [ROUTE_DEF_RETAIN_HDR] = BIT(27), 94 [ROUTE_DIS] = BIT(28), 95 /* Bits 29-31 reserved */ 96 }; 97 98 REG_FIELDS(ROUTE, route, 0x00000054); 99 100 static const u32 reg_shared_mem_size_fmask[] = { 101 [MEM_SIZE] = GENMASK(15, 0), 102 [MEM_BADDR] = GENMASK(31, 16), 103 }; 104 105 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x0000005c); 106 107 static const u32 reg_qsb_max_writes_fmask[] = { 108 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 109 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 110 /* Bits 8-31 reserved */ 111 }; 112 113 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000070); 114 115 static const u32 reg_qsb_max_reads_fmask[] = { 116 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 117 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 118 /* Bits 8-15 reserved */ 119 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 120 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 121 }; 122 123 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000074); 124 125 /* Valid bits defined by ipa->available */ 126 127 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000120, 0x0004); 128 129 static const u32 reg_filt_rout_cache_flush_fmask[] = { 130 [ROUTER_CACHE] = BIT(0), 131 /* Bits 1-3 reserved */ 132 [FILTER_CACHE] = BIT(4), 133 /* Bits 5-31 reserved */ 134 }; 135 136 REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404); 137 138 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 139 [IPA_BASE_ADDR] = GENMASK(17, 0), 140 /* Bits 18-31 reserved */ 141 }; 142 143 /* Offset must be a multiple of 8 */ 144 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478); 145 146 static const u32 reg_ipa_tx_cfg_fmask[] = { 147 /* Bits 0-1 reserved */ 148 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 149 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 150 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 151 [DMAW_MAX_BEATS_256_DIS] = BIT(11), 152 [PA_MASK_EN] = BIT(12), 153 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 154 [DUAL_TX_ENABLE] = BIT(17), 155 [SSPND_PA_NO_START_STATE] = BIT(18), 156 /* Bit 19 reserved */ 157 [HOLB_STICKY_DROP_EN] = BIT(20), 158 /* Bits 21-31 reserved */ 159 }; 160 161 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488); 162 163 static const u32 reg_idle_indication_cfg_fmask[] = { 164 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 165 [CONST_NON_IDLE_ENABLE] = BIT(16), 166 /* Bits 17-31 reserved */ 167 }; 168 169 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8); 170 171 static const u32 reg_qtime_timestamp_cfg_fmask[] = { 172 /* Bits 0-7 reserved */ 173 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 174 /* Bits 13-15 reserved */ 175 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 176 /* Bits 21-31 reserved */ 177 }; 178 179 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac); 180 181 static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { 182 [DIV_VALUE] = GENMASK(8, 0), 183 /* Bits 9-30 reserved */ 184 [DIV_ENABLE] = BIT(31), 185 }; 186 187 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0); 188 189 static const u32 reg_timers_pulse_gran_cfg_fmask[] = { 190 [PULSE_GRAN_0] = GENMASK(2, 0), 191 [PULSE_GRAN_1] = GENMASK(5, 3), 192 [PULSE_GRAN_2] = GENMASK(8, 6), 193 [PULSE_GRAN_3] = GENMASK(11, 9), 194 /* Bits 12-31 reserved */ 195 }; 196 197 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4); 198 199 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 200 [X_MIN_LIM] = GENMASK(5, 0), 201 /* Bits 6-7 reserved */ 202 [X_MAX_LIM] = GENMASK(13, 8), 203 /* Bits 14-15 reserved */ 204 [Y_MIN_LIM] = GENMASK(21, 16), 205 /* Bits 22-23 reserved */ 206 [Y_MAX_LIM] = GENMASK(29, 24), 207 /* Bits 30-31 reserved */ 208 }; 209 210 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 211 0x00000500, 0x0020); 212 213 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 214 [X_MIN_LIM] = GENMASK(5, 0), 215 /* Bits 6-7 reserved */ 216 [X_MAX_LIM] = GENMASK(13, 8), 217 /* Bits 14-15 reserved */ 218 [Y_MIN_LIM] = GENMASK(21, 16), 219 /* Bits 22-23 reserved */ 220 [Y_MAX_LIM] = GENMASK(29, 24), 221 /* Bits 30-31 reserved */ 222 }; 223 224 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 225 0x00000504, 0x0020); 226 227 static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = { 228 [X_MIN_LIM] = GENMASK(5, 0), 229 /* Bits 6-7 reserved */ 230 [X_MAX_LIM] = GENMASK(13, 8), 231 /* Bits 14-15 reserved */ 232 [Y_MIN_LIM] = GENMASK(21, 16), 233 /* Bits 22-23 reserved */ 234 [Y_MAX_LIM] = GENMASK(29, 24), 235 /* Bits 30-31 reserved */ 236 }; 237 238 REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, 239 0x00000508, 0x0020); 240 241 static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = { 242 [X_MIN_LIM] = GENMASK(5, 0), 243 /* Bits 6-7 reserved */ 244 [X_MAX_LIM] = GENMASK(13, 8), 245 /* Bits 14-15 reserved */ 246 [Y_MIN_LIM] = GENMASK(21, 16), 247 /* Bits 22-23 reserved */ 248 [Y_MAX_LIM] = GENMASK(29, 24), 249 /* Bits 30-31 reserved */ 250 }; 251 252 REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, 253 0x0000050c, 0x0020); 254 255 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 256 [X_MIN_LIM] = GENMASK(5, 0), 257 /* Bits 6-7 reserved */ 258 [X_MAX_LIM] = GENMASK(13, 8), 259 /* Bits 14-15 reserved */ 260 [Y_MIN_LIM] = GENMASK(21, 16), 261 /* Bits 22-23 reserved */ 262 [Y_MAX_LIM] = GENMASK(29, 24), 263 /* Bits 30-31 reserved */ 264 }; 265 266 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 267 0x00000600, 0x0020); 268 269 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 270 [X_MIN_LIM] = GENMASK(5, 0), 271 /* Bits 6-7 reserved */ 272 [X_MAX_LIM] = GENMASK(13, 8), 273 /* Bits 14-15 reserved */ 274 [Y_MIN_LIM] = GENMASK(21, 16), 275 /* Bits 22-23 reserved */ 276 [Y_MAX_LIM] = GENMASK(29, 24), 277 /* Bits 30-31 reserved */ 278 }; 279 280 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 281 0x00000604, 0x0020); 282 283 static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { 284 [X_MIN_LIM] = GENMASK(5, 0), 285 /* Bits 6-7 reserved */ 286 [X_MAX_LIM] = GENMASK(13, 8), 287 /* Bits 14-15 reserved */ 288 [Y_MIN_LIM] = GENMASK(21, 16), 289 /* Bits 22-23 reserved */ 290 [Y_MAX_LIM] = GENMASK(29, 24), 291 /* Bits 30-31 reserved */ 292 }; 293 294 REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, 295 0x00000608, 0x0020); 296 297 static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { 298 [X_MIN_LIM] = GENMASK(5, 0), 299 /* Bits 6-7 reserved */ 300 [X_MAX_LIM] = GENMASK(13, 8), 301 /* Bits 14-15 reserved */ 302 [Y_MIN_LIM] = GENMASK(21, 16), 303 /* Bits 22-23 reserved */ 304 [Y_MAX_LIM] = GENMASK(29, 24), 305 /* Bits 30-31 reserved */ 306 }; 307 308 REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, 309 0x0000060c, 0x0020); 310 311 /* Valid bits defined by ipa->available */ 312 313 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004); 314 315 static const u32 reg_endp_init_cfg_fmask[] = { 316 [FRAG_OFFLOAD_EN] = BIT(0), 317 [CS_OFFLOAD_EN] = GENMASK(2, 1), 318 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 319 /* Bit 7 reserved */ 320 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 321 [PIPE_REPLICATE_EN] = BIT(9), 322 /* Bits 10-31 reserved */ 323 }; 324 325 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080); 326 327 static const u32 reg_endp_init_nat_fmask[] = { 328 [NAT_EN] = GENMASK(1, 0), 329 /* Bits 2-31 reserved */ 330 }; 331 332 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080); 333 334 static const u32 reg_endp_init_hdr_fmask[] = { 335 [HDR_LEN] = GENMASK(5, 0), 336 [HDR_OFST_METADATA_VALID] = BIT(6), 337 [HDR_OFST_METADATA] = GENMASK(12, 7), 338 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 339 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 340 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 341 /* Bit 26 reserved */ 342 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 343 [HDR_LEN_MSB] = GENMASK(29, 28), 344 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 345 }; 346 347 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080); 348 349 static const u32 reg_endp_init_hdr_ext_fmask[] = { 350 [HDR_ENDIANNESS] = BIT(0), 351 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 352 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 353 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 354 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 355 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 356 /* Bits 14-15 reserved */ 357 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 358 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 359 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 360 [HDR_BYTES_TO_REMOVE_VALID] = BIT(22), 361 /* Bit 23 reserved */ 362 [HDR_BYTES_TO_REMOVE] = GENMASK(31, 24), 363 }; 364 365 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080); 366 367 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 368 0x00001018, 0x0080); 369 370 static const u32 reg_endp_init_mode_fmask[] = { 371 [ENDP_MODE] = GENMASK(2, 0), 372 [DCPH_ENABLE] = BIT(3), 373 [DEST_PIPE_INDEX] = GENMASK(11, 4), 374 [BYTE_THRESHOLD] = GENMASK(27, 12), 375 /* Bit 28 reserved */ 376 [PAD_EN] = BIT(29), 377 [DRBIP_ACL_ENABLE] = BIT(30), 378 /* Bit 31 reserved */ 379 }; 380 381 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080); 382 383 static const u32 reg_endp_init_aggr_fmask[] = { 384 [AGGR_EN] = GENMASK(1, 0), 385 [AGGR_TYPE] = GENMASK(4, 2), 386 [BYTE_LIMIT] = GENMASK(10, 5), 387 /* Bit 11 reserved */ 388 [TIME_LIMIT] = GENMASK(16, 12), 389 [PKT_LIMIT] = GENMASK(22, 17), 390 [SW_EOF_ACTIVE] = BIT(23), 391 [FORCE_CLOSE] = BIT(24), 392 /* Bit 25 reserved */ 393 [HARD_BYTE_LIMIT_EN] = BIT(26), 394 [AGGR_GRAN_SEL] = BIT(27), 395 [AGGR_COAL_L2] = BIT(28), 396 /* Bits 27-31 reserved */ 397 }; 398 399 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080); 400 401 static const u32 reg_endp_init_hol_block_en_fmask[] = { 402 [HOL_BLOCK_EN] = BIT(0), 403 /* Bits 1-31 reserved */ 404 }; 405 406 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 407 0x0000102c, 0x0080); 408 409 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 410 [TIMER_LIMIT] = GENMASK(4, 0), 411 /* Bits 5-7 reserved */ 412 [TIMER_GRAN_SEL] = GENMASK(9, 8), 413 /* Bits 10-31 reserved */ 414 }; 415 416 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 417 0x00001030, 0x0080); 418 419 static const u32 reg_endp_init_deaggr_fmask[] = { 420 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 421 [SYSPIPE_ERR_DETECTION] = BIT(6), 422 [PACKET_OFFSET_VALID] = BIT(7), 423 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 424 [IGNORE_MIN_PKT_ERR] = BIT(14), 425 /* Bit 15 reserved */ 426 [MAX_PACKET_LEN] = GENMASK(31, 16), 427 }; 428 429 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080); 430 431 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 432 [ENDP_RSRC_GRP] = GENMASK(2, 0), 433 /* Bits 3-31 reserved */ 434 }; 435 436 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080); 437 438 static const u32 reg_endp_init_seq_fmask[] = { 439 [SEQ_TYPE] = GENMASK(7, 0), 440 /* Bits 8-31 reserved */ 441 }; 442 443 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080); 444 445 static const u32 reg_endp_status_fmask[] = { 446 [STATUS_EN] = BIT(0), 447 [STATUS_ENDP] = GENMASK(8, 1), 448 [STATUS_PKT_SUPPRESS] = BIT(9), 449 /* Bits 10-31 reserved */ 450 }; 451 452 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080); 453 454 static const u32 reg_endp_filter_cache_cfg_fmask[] = { 455 [CACHE_MSK_SRC_ID] = BIT(0), 456 [CACHE_MSK_SRC_IP] = BIT(1), 457 [CACHE_MSK_DST_IP] = BIT(2), 458 [CACHE_MSK_SRC_PORT] = BIT(3), 459 [CACHE_MSK_DST_PORT] = BIT(4), 460 [CACHE_MSK_PROTOCOL] = BIT(5), 461 [CACHE_MSK_METADATA] = BIT(6), 462 /* Bits 7-31 reserved */ 463 }; 464 465 REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg, 466 0x0000105c, 0x0080); 467 468 static const u32 reg_endp_router_cache_cfg_fmask[] = { 469 [CACHE_MSK_SRC_ID] = BIT(0), 470 [CACHE_MSK_SRC_IP] = BIT(1), 471 [CACHE_MSK_DST_IP] = BIT(2), 472 [CACHE_MSK_SRC_PORT] = BIT(3), 473 [CACHE_MSK_DST_PORT] = BIT(4), 474 [CACHE_MSK_PROTOCOL] = BIT(5), 475 [CACHE_MSK_METADATA] = BIT(6), 476 /* Bits 7-31 reserved */ 477 }; 478 479 REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg, 480 0x00001060, 0x0080); 481 482 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 483 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP); 484 485 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 486 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP); 487 488 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 489 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP); 490 491 static const u32 reg_ipa_irq_uc_fmask[] = { 492 [UC_INTR] = BIT(0), 493 /* Bits 1-31 reserved */ 494 }; 495 496 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP); 497 498 /* Valid bits defined by ipa->available */ 499 500 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 501 0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004); 502 503 /* Valid bits defined by ipa->available */ 504 505 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 506 0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004); 507 508 /* Valid bits defined by ipa->available */ 509 510 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 511 0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004); 512 513 static const struct reg *reg_array[] = { 514 [COMP_CFG] = ®_comp_cfg, 515 [CLKON_CFG] = ®_clkon_cfg, 516 [ROUTE] = ®_route, 517 [SHARED_MEM_SIZE] = ®_shared_mem_size, 518 [QSB_MAX_WRITES] = ®_qsb_max_writes, 519 [QSB_MAX_READS] = ®_qsb_max_reads, 520 [FILT_ROUT_CACHE_FLUSH] = ®_filt_rout_cache_flush, 521 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 522 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 523 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 524 [IPA_TX_CFG] = ®_ipa_tx_cfg, 525 [FLAVOR_0] = ®_flavor_0, 526 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 527 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, 528 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, 529 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, 530 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 531 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 532 [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type, 533 [SRC_RSRC_GRP_67_RSRC_TYPE] = ®_src_rsrc_grp_67_rsrc_type, 534 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 535 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 536 [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type, 537 [DST_RSRC_GRP_67_RSRC_TYPE] = ®_dst_rsrc_grp_67_rsrc_type, 538 [ENDP_INIT_CFG] = ®_endp_init_cfg, 539 [ENDP_INIT_NAT] = ®_endp_init_nat, 540 [ENDP_INIT_HDR] = ®_endp_init_hdr, 541 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 542 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 543 [ENDP_INIT_MODE] = ®_endp_init_mode, 544 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 545 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 546 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 547 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 548 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 549 [ENDP_INIT_SEQ] = ®_endp_init_seq, 550 [ENDP_STATUS] = ®_endp_status, 551 [ENDP_FILTER_CACHE_CFG] = ®_endp_filter_cache_cfg, 552 [ENDP_ROUTER_CACHE_CFG] = ®_endp_router_cache_cfg, 553 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 554 [IPA_IRQ_EN] = ®_ipa_irq_en, 555 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 556 [IPA_IRQ_UC] = ®_ipa_irq_uc, 557 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 558 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 559 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 560 }; 561 562 const struct regs ipa_regs_v5_5 = { 563 .reg_count = ARRAY_SIZE(reg_array), 564 .reg = reg_array, 565 }; 566