Lines Matching +full:29 +full:- +full:bit
1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
46 #define MT_RXD1_NORMAL_ICV_ERR BIT(25)
47 #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
49 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
50 #define MT_RXD1_NORMAL_ADD_OM BIT(30)
51 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
56 #define MT_RXD2_NORMAL_HDR_TRANS BIT(7)
59 #define MT_RXD2_NORMAL_MU_BAR BIT(21)
60 #define MT_RXD2_NORMAL_SW_BIT BIT(22)
61 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
62 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
63 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
64 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
65 #define MT_RXD2_NORMAL_FRAG BIT(27)
66 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
67 #define MT_RXD2_NORMAL_NDATA BIT(29)
68 #define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
69 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
75 #define MT_RXD3_NORMAL_U2M BIT(0)
76 #define MT_RXD3_NORMAL_HTC_VLD BIT(18)
77 #define MT_RXD3_NORMAL_BEACON_MC BIT(20)
78 #define MT_RXD3_NORMAL_BEACON_UC BIT(21)
79 #define MT_RXD3_NORMAL_CO_ANT BIT(22)
80 #define MT_RXD3_NORMAL_FCS_ERR BIT(24)
81 #define MT_RXD3_NORMAL_IP_SUM BIT(26)
82 #define MT_RXD3_NORMAL_UDP_TCP_SUM BIT(27)
83 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
88 #define MT_RXD4_MID_AMSDU_FRAME BIT(1)
89 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
91 #define MT_RXV_HDR_BAND_IDX BIT(24)
101 /* P-RXV */
103 #define MT_PRXV_TX_DCM BIT(4)
104 #define MT_PRXV_TX_ER_SU_106T BIT(5)
106 #define MT_PRXV_TXBF BIT(11)
107 #define MT_PRXV_HT_AD_CODE BIT(12)
117 #define MT_PRXV_DCM BIT(5)
119 /* C-RXV */
122 #define MT_CRXV_HE_LDPC_EXT_SYM BIT(30)
124 #define MT_CRXV_HE_PE_DISAMBIG BIT(1)
125 #define MT_CRXV_HE_UPLINK BIT(2)
128 #define MT_CRXV_HE_BEAM_CHNG BIT(29)
130 #define MT_CRXV_HE_DOPPLER BIT(0)
147 #define MT_CRXV_EHT_LDPC_EXT_SYM BIT(30)
148 #define MT_CRXV_EHT_PE_DISAMBIG BIT(1)
149 #define MT_CRXV_EHT_UPLINK BIT(2)
151 #define MT_CRXV_EHT_BEAM_CHNG BIT(29)
152 #define MT_CRXV_EHT_DOPPLER BIT(0)
207 #define MT_CT_INFO_APPLY_TXD BIT(0)
208 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
209 #define MT_CT_INFO_MGMT_FRAME BIT(2)
210 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
211 #define MT_CT_INFO_HSR2_TX BIT(4)
212 #define MT_CT_INFO_FROM_HOST BIT(7)
221 #define MT_TXD1_FIXED_RATE BIT(31)
224 #define MT_TXD1_BIP BIT(24)
225 #define MT_TXD1_ETH_802_3 BIT(20)
234 #define MT_TXD2_HTC_VLD BIT(13)
235 #define MT_TXD2_DURATION BIT(12)
237 #define MT_TXD2_RTS BIT(9)
238 #define MT_TXD2_OWN_MAC_MAP BIT(8)
243 #define MT_TXD3_SN_VALID BIT(31)
244 #define MT_TXD3_PN_VALID BIT(30)
245 #define MT_TXD3_SW_POWER_MGMT BIT(29)
246 #define MT_TXD3_BA_DISABLE BIT(28)
250 #define MT_TXD3_HW_AMSDU BIT(5)
251 #define MT_TXD3_BCM BIT(4)
252 #define MT_TXD3_EEOSP BIT(3)
253 #define MT_TXD3_EMRD BIT(2)
254 #define MT_TXD3_PROTECT_FRAME BIT(1)
255 #define MT_TXD3_NO_ACK BIT(0)
260 #define MT_TXD5_FL BIT(15)
261 #define MT_TXD5_BYPASS_TBB BIT(14)
262 #define MT_TXD5_BYPASS_RBB BIT(13)
263 #define MT_TXD5_BSS_COLOR_ZERO BIT(12)
264 #define MT_TXD5_TX_STATUS_HOST BIT(10)
265 #define MT_TXD5_TX_STATUS_MCU BIT(9)
266 #define MT_TXD5_TX_STATUS_FMT BIT(8)
270 #define MT_TXD6_VTA BIT(28)
271 #define MT_TXD6_FIXED_BW BIT(25)
274 #define MT_TXD6_TIMESTAMP_OFS_EN BIT(15)
278 #define MT_TXD6_DIS_MAT BIT(3)
279 #define MT_TXD6_DAS BIT(2)
280 #define MT_TXD6_AMSDU_CAP BIT(1)
283 #define MT_TXD7_IP_SUM BIT(29)
284 #define MT_TXD7_DROP_BY_SDO BIT(28)
285 #define MT_TXD7_MAC_TXD BIT(27)
286 #define MT_TXD7_CTXD BIT(26)
288 #define MT_TXD7_UDP_TCP_SUM BIT(15)
296 #define MT_TX_RATE_STBC BIT(14)
299 #define MT_TX_RATE_SU_EXT_TONE BIT(5)
300 #define MT_TX_RATE_DCM BIT(4)
301 /* VHT/HE only use bits 0-3 */
310 #define MT_TXFREE_INFO_PAIR BIT(31)
311 #define MT_TXFREE_INFO_HEADER BIT(30)
315 #define MT_TXFREE_INFO_STAT GENMASK(29, 28)
317 #define MT_TXS0_BW GENMASK(31, 29)
319 #define MT_TXS0_AMPDU BIT(25)
321 #define MT_TXS0_BA_ERROR BIT(22)
322 #define MT_TXS0_PS_FLAG BIT(21)
323 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
324 #define MT_TXS0_BIP_ERROR BIT(19)
326 #define MT_TXS0_QUEUE_TIMEOUT BIT(18)
327 #define MT_TXS0_RTS_TIMEOUT BIT(17)
328 #define MT_TXS0_ACK_TIMEOUT BIT(16)
331 #define MT_TXS0_TX_STATUS_HOST BIT(15)
332 #define MT_TXS0_TX_STATUS_MCU BIT(14)
341 #define MT_TXS2_BAND GENMASK(29, 28)
346 #define MT_TXS3_RATE_STBC BIT(7)
347 #define MT_TXS3_FIXED_RATE BIT(6)
349 #define MT_TXS3_SHARED_ANTENNA BIT(3)
355 #define MT_TXS5_F0_FINAL_MPDU BIT(31)
356 #define MT_TXS5_F0_QOS BIT(30)
357 #define MT_TXS5_F0_TX_COUNT GENMASK(29, 25)
378 #define MT_TXS5_MPDU_TX_BYTE_SCALE BIT(15)
382 #define MT_TXS6_MPDU_FAIL_BYTE_SCALE BIT(15)
386 #define MT_TXS7_MPDU_RETRY_BYTE_SCALE BIT(15)