Lines Matching +full:29 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * LDOs on the device are disabled if CSI-2 module is powered on
25 * Errata does not apply when CSI-2 module is powered off
30 * which is essentially CSI2 REG10 bit 6:
35 #define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
106 #define CAL_HL_HWINFO_NPPI_CTXS0_MASK GENMASK(29, 28)
113 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK BIT(0)
124 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK BIT(0)
128 #define CAL_HL_IRQ_WDMA_END_MASK(m) BIT(m)
129 #define CAL_HL_IRQ_WDMA_START_MASK(m) BIT(m)
131 #define CAL_HL_IRQ_OCPO_ERR_MASK BIT(6)
133 #define CAL_HL_IRQ_CIO_MASK(i) BIT(16 + (i) * 8)
134 #define CAL_HL_IRQ_VC_MASK(i) BIT(17 + (i) * 8)
136 #define CAL_PIX_PROC_EN_MASK BIT(0)
182 #define CAL_CTRL_POSTED_WRITES_MASK BIT(0)
193 #define CAL_CTRL_PWRSCPCLK_MASK BIT(21)
196 #define CAL_CTRL_RD_DMA_STALL_MASK BIT(22)
216 #define CAL_LINE_NUMBER_EVT_MASK GENMASK(29, 16)
221 #define CAL_VPORT_CTRL1_WIDTH_MASK BIT(31)
226 #define CAL_VPORT_CTRL2_FREERUNNING_MASK BIT(15)
229 #define CAL_VPORT_CTRL2_FS_RESETS_MASK BIT(16)
232 #define CAL_VPORT_CTRL2_FSM_RESET_MASK BIT(17)
240 #define CAL_BYS_CTRL1_BYSINEN_MASK BIT(31)
244 #define CAL_BYS_CTRL2_DUPLICATEDDATA_MASK BIT(10)
247 #define CAL_BYS_CTRL2_FREERUNNING_MASK BIT(11)
251 #define CAL_RD_DMA_CTRL_GO_MASK BIT(0)
256 #define CAL_RD_DMA_CTRL_INIT_MASK BIT(1)
267 #define CAL_RD_DMA_YSIZE_MASK GENMASK(29, 16)
280 #define CAL_RD_DMA_CTRL2_ICM_CSTART_MASK BIT(3)
286 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK BIT(6)
289 #define CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK GENMASK(29, 16)
303 #define CAL_WR_DMA_CTRL_ICM_PSTART_MASK BIT(5)
314 #define CAL_WR_DMA_CTRL_STALL_RD_MASK BIT(14)
330 #define CAL_CSI2_PPI_CTRL_IF_EN_MASK BIT(0)
331 #define CAL_CSI2_PPI_CTRL_ECC_EN_MASK BIT(2)
332 #define CAL_CSI2_PPI_CTRL_FRAME_MASK BIT(3)
343 #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK BIT(3)
347 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK BIT(7)
349 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK BIT(11)
351 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK BIT(15)
353 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK BIT(19)
354 #define CAL_CSI2_COMPLEXIO_CFG_PWR_AUTO_MASK BIT(24)
363 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK BIT(29)
366 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK BIT(30)
372 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS1_MASK BIT(0)
373 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS2_MASK BIT(1)
374 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS3_MASK BIT(2)
375 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS4_MASK BIT(3)
376 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS5_MASK BIT(4)
377 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1_MASK BIT(5)
378 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2_MASK BIT(6)
379 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3_MASK BIT(7)
380 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4_MASK BIT(8)
381 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5_MASK BIT(9)
382 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC1_MASK BIT(10)
383 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC2_MASK BIT(11)
384 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC3_MASK BIT(12)
385 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC4_MASK BIT(13)
386 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC5_MASK BIT(14)
387 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL1_MASK BIT(15)
388 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL2_MASK BIT(16)
389 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK BIT(17)
390 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK BIT(18)
391 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK BIT(19)
393 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK BIT(20)
394 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK BIT(21)
395 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK BIT(22)
396 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM4_MASK BIT(23)
397 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM5_MASK BIT(24)
398 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER_MASK BIT(25)
399 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT_MASK BIT(26)
400 #define CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK BIT(27)
401 #define CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK BIT(28)
402 #define CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK BIT(30)
405 #define CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK BIT(13)
406 #define CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK BIT(14)
407 #define CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK BIT(15)
409 #define CAL_CSI2_VC_IRQ_FS_IRQ_MASK(n) BIT(0 + ((n) * 8))
410 #define CAL_CSI2_VC_IRQ_FE_IRQ_MASK(n) BIT(1 + ((n) * 8))
411 #define CAL_CSI2_VC_IRQ_LS_IRQ_MASK(n) BIT(2 + ((n) * 8))
412 #define CAL_CSI2_VC_IRQ_LE_IRQ_MASK(n) BIT(3 + ((n) * 8))
413 #define CAL_CSI2_VC_IRQ_CS_IRQ_MASK(n) BIT(4 + ((n) * 8))
414 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION_IRQ_MASK(n) BIT(5 + ((n) * 8))
421 #define CAL_CSI2_CTX_ATT_MASK BIT(13)
424 #define CAL_CSI2_CTX_PACK_MODE_MASK BIT(14)
427 #define CAL_CSI2_CTX_LINES_MASK GENMASK(29, 16)
433 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK BIT(24)
441 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_MASK BIT(25)
444 #define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK GENMASK(29, 28)
446 #define CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK BIT(6)
451 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK GENMASK(29, 28)
454 #define CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK BIT(0)
457 #define CM_CAMERRX_CTRL_CSI1_MODE_MASK BIT(5)
458 #define CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK BIT(10)
461 #define CM_CAMERRX_CTRL_CSI0_MODE_MASK BIT(17)