emulex/benet/be_hw.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2005-2016 Broadcom.
7  * linux-drivers@emulex.com
18  * for the MAILBOX structure. Software must poll the ready bit until this
20  * bits in the address. It must poll the ready bit until the command is
25 #define MPU_MAILBOX_DB_RDY_MASK	0x1 	/* bit 0 */
26 #define MPU_MAILBOX_DB_HI_MASK	0x2	/* bit 1 */
33 #define SLIPORT_SEMAPHORE_OFFSET_SH		0x94  /* PCI-CFG offset */
40 #define SLIPORT_SOFTRESET_SR_MASK		0x00000080	/* SR bit */
44 #define POST_STAGE_HOST_RDY 		0x2 /* Host has given go-ahed to FW */
79  * atomically without having to arbitrate for the PCI Interrupt Disable bit
82 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK	BIT(29) /* bit 29 */
127 #define DB_EQ_RING_ID_MASK		0x1FF	/* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK		0x3e00  /* bits 9-13 */
129 #define DB_EQ_RING_ID_EXT_MASK_SHIFT	(2) /* qid bits 9-13 placing at 11-15 */
132 #define DB_EQ_CLR_SHIFT			(9)	/* bit 9 */
134 #define DB_EQ_EVNT_SHIFT		(10)	/* bit 10 */
136 #define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
137 /* Rearm bit */
138 #define DB_EQ_REARM_SHIFT		(29)	/* bit 29 */
140 #define DB_EQ_R2I_DLY_SHIFT		(30)    /* bits 30 - 31 */
154 #define DB_CQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
155 #define DB_CQ_RING_ID_EXT_MASK		0x7C00	/* bits 10-14 */
156 #define DB_CQ_RING_ID_EXT_MASK_SHIFT	(1)	/* qid bits 10-14
157 						 placing at 11-15 */
160 #define DB_CQ_NUM_POPPED_SHIFT		(16) 	/* bits 16 - 28 */
161 /* Rearm bit */
162 #define DB_CQ_REARM_SHIFT		(29) 	/* bit 29 */
166 #define DB_TXULP_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
168 #define DB_TXULP_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
169 #define DB_TXULP_NUM_POSTED_MASK	0x3FFF	/* bits 16 - 29 */
173 #define DB_RQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
175 #define DB_RQ_NUM_POSTED_SHIFT		(24)	/* bits 24 - 31 */
179 #define DB_MCCQ_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
181 #define DB_MCCQ_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
201 #define EQ_ENTRY_VALID_MASK 		0x1	/* bit 0 */
202 #define EQ_ENTRY_RES_ID_MASK 		0xFFFF	/* bits 16 - 31 */
215 	__le32 frag_len;		/* dword 3: bits 0 - 15 */
218 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
243 #define TX_HDR_WRB_EVT			BIT(1)		/* word 2 */
266 /* Pseudo amap definition for eth_tx_compl in which each bit of the
300  * each bit of the actual structure is defined as a byte: used to calculate
334  * each bit of the actual structure is defined as a byte: used to calculate