| /linux-6.12.1/Documentation/input/devices/ |
| D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
6 Extra information for hardware version 1 found and
15 1. Introduction
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
31 6.2.1 One/Three finger touch
33 7. Hardware version 4
36 7.2.1 Status packet
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/alderlake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
6 "Deprecated": "1",
15 "Counter": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
19 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
26 "Counter": "0,1,2,3,4,5,6,7",
27 "CounterMask": "1",
28 "Deprecated": "1",
37 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/meteorlake/ |
| D | pipeline.json | 3 "BriefDescription": "Counts the number of cycles when any of the dividers are active.",
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
14 "Counter": "0,1,2,3,4,5,6,7",
15 "CounterMask": "1",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
25 "Counter": "0,1,2,3,4,5,6,7",
26 "CounterMask": "1",
34 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
35 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| D | floating-point.json | 3 …"BriefDescription": "Counts the number of cycles when any of the floating point dividers are activ…
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
14 "Counter": "0,1,2,3,4,5,6,7",
15 "CounterMask": "1",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux-6.12.1/drivers/net/ethernet/sfc/ |
| D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
14 #define MC_FW_STATE_POR (1)
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
54 /* The current version of the MCDI protocol.
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/graniterapids/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
14 "Counter": "0,1,2,3,4,5,6,7",
15 "CounterMask": "1",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBS": "1",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/alderlaken/ |
| D | pipeline.json | 3 …"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
4 "Counter": "0,1,2,3,4,5",
7 "PEBS": "1",
8 …"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP…
13 "Counter": "0,1,2,3,4,5",
14 "Deprecated": "1",
17 "PEBS": "1",
22 …"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructio…
23 "Counter": "0,1,2,3,4,5",
26 "PEBS": "1",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PEBS": "1",
32 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBS": "1",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
6 "Deprecated": "1",
14 "Counter": "0,1,2,3,4,5,6,7",
15 "CounterMask": "1",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
24 "Counter": "0,1,2,3,4,5,6,7",
25 "CounterMask": "1",
26 "Deprecated": "1",
34 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
6 "Deprecated": "1",
14 "Counter": "0,1,2,3,4,5,6,7",
15 "CounterMask": "1",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
24 "Counter": "0,1,2,3,4,5,6,7",
25 "CounterMask": "1",
26 "Deprecated": "1",
34 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/sfc/siena/ |
| D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
14 #define MC_FW_STATE_POR (1)
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
54 /* The current version of the MCDI protocol.
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/icelake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PEBS": "1",
32 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBS": "1",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/rocketlake/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PEBS": "1",
32 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBS": "1",
[all …]
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| /linux-6.12.1/include/uapi/drm/ |
| D | drm_fourcc.h | 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
8 * and/or sell copies of the Software, and to permit persons to whom the
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PEBS": "1",
32 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBS": "1",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/sierraforest/ |
| D | pipeline.json | 3 "BriefDescription": "Counts the number of cycles when any of the dividers are active.",
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
12 …"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
13 "Counter": "0,1,2,3,4,5,6,7",
16 …"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP…
20 …"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructio…
21 "Counter": "0,1,2,3,4,5,6,7",
28 …"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions…
29 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| D | cache.json | 3 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o…
4 "Counter": "0,1,2,3,4,5,6,7",
7 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C…
12 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on…
13 "Counter": "0,1,2,3,4,5,6,7",
16 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca…
21 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instr…
22 "Counter": "0,1,2,3,4,5,6,7",
29 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o…
30 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/grandridge/ |
| D | pipeline.json | 3 "BriefDescription": "Counts the number of cycles when any of the dividers are active.",
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
12 …"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
13 "Counter": "0,1,2,3,4,5,6,7",
16 …"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP…
20 …"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructio…
21 "Counter": "0,1,2,3,4,5,6,7",
28 …"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions…
29 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| D | cache.json | 3 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o…
4 "Counter": "0,1,2,3,4,5,6,7",
7 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C…
12 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on…
13 "Counter": "0,1,2,3,4,5,6,7",
16 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca…
21 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instr…
22 "Counter": "0,1,2,3,4,5,6,7",
29 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o…
30 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux-6.12.1/arch/xtensa/variants/dc233c/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2010 Tensilica Inc.
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
17 distribute, sublicense, and/or sell copies of the Software, and to
22 in all copies or substantial portions of the Software.
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
[all …]
|
| /linux-6.12.1/arch/alpha/lib/ |
| D | ev6-memset.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
5 * This is an efficient (and relatively small) implementation of the C library
6 * "memset()" function for the 21264 implementation of Alpha.
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
10 * Much of the information about 21264 scheduling/coding comes from:
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/scsi/ |
| D | hisilicon-sas.txt | 6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
12 register. The second is the address and length of CPLD register for
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
[all …]
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| /linux-6.12.1/arch/xtensa/variants/test_kc705_be/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
17 distribute, sublicense, and/or sell copies of the Software, and to
22 in all copies or substantial portions of the Software.
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
[all …]
|
| /linux-6.12.1/Documentation/userspace-api/media/v4l/ |
| D | pixfmt-yuv-planar.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. planar-yuv:
12 - Semi-planar formats use two planes. The first plane is the luma plane and
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
20 tiled. Padding may be supported at the end of the lines, and the line stride of
21 the chroma planes may be constrained by the line stride of the luma plane.
26 and applications that support the multi-planar API, described in
27 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
31 Semi-Planar YUV Formats
40 For memory contiguous formats, the number of padding pixels at the end of the
[all …]
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| /linux-6.12.1/arch/xtensa/variants/dc232b/include/variant/ |
| D | tie.h | 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 * Copyright (C) 1999-2007 Tensilica Inc.
16 #define XCHAL_CP_NUM 1 /* number of coprocessors */
17 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
18 #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
19 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
21 /* Basic parameters of each coprocessor: */
24 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
25 #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
[all …]
|