include/variant/tie.h

2  * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
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35 #define XCHAL_CP_NUM			1	/* number of coprocessors */
36 #define XCHAL_CP_MAX			8	/* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK			0x80	/* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK		0x80	/* bitmask of only port CPs */
40 /*  Basic parameters of each coprocessor:  */
43 #define XCHAL_CP7_SA_SIZE		0	/* size of state save area */
44 #define XCHAL_CP7_SA_ALIGN		1	/* min alignment of save area */
49 #define XCHAL_CP0_SA_ALIGN		1
51 #define XCHAL_CP1_SA_ALIGN		1
53 #define XCHAL_CP2_SA_ALIGN		1
55 #define XCHAL_CP3_SA_ALIGN		1
57 #define XCHAL_CP4_SA_ALIGN		1
59 #define XCHAL_CP5_SA_ALIGN		1
61 #define XCHAL_CP6_SA_ALIGN		1
63 /*  Save area for non-coprocessor optional and custom (TIE) state:  */
65 #define XCHAL_NCP_SA_ALIGN		4
68 #define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
69 #define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
72  * Detailed contents of save areas.
81  *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
82  *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
83  *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
85  *	galign = group byte alignment (power of 2) (galign >= align)
86  *	align = register byte alignment (power of 2)
89  *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
91  *	regnum = reg index in regfile, or special/TIE-user reg number
92  *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
94  *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
98  *  To filter out certain registers, e.g. to expand only the non-global
113  XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
114  XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
115  XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
116  XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
117  XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
118  XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
119  XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
120  XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0)
146 /* Byte length of instruction from its first nibble (op0 field), per FLIX.  */