Lines Matching +full:1 +full:- +full:of +full:- +full:4
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
6 "Deprecated": "1",
15 "Counter": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
19 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
26 "Counter": "0,1,2,3,4,5,6,7",
27 "CounterMask": "1",
28 "Deprecated": "1",
37 "Counter": "0,1,2,3,4,5,6,7",
38 "CounterMask": "1",
47 "Counter": "0,1,2,3,4,5,6,7",
48 "CounterMask": "1",
49 "Deprecated": "1",
57 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
58 "Counter": "0,1,2,3,4,5,6,7",
61 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
67 …"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
68 "Counter": "0,1,2,3,4,5",
71 "PEBS": "1",
72 …"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP…
78 "Counter": "0,1,2,3,4,5,6,7",
81 "PEBS": "1",
88 "Counter": "0,1,2,3,4,5",
89 "Deprecated": "1",
92 "PEBS": "1",
98 …"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructio…
99 "Counter": "0,1,2,3,4,5",
102 "PEBS": "1",
109 "Counter": "0,1,2,3,4,5,6,7",
112 "PEBS": "1",
120 "Counter": "0,1,2,3,4,5,6,7",
123 "PEBS": "1",
130 …"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions…
131 "Counter": "0,1,2,3,4,5",
134 "PEBS": "1",
141 "Counter": "0,1,2,3,4,5,6,7",
144 "PEBS": "1",
151 …"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far …
152 "Counter": "0,1,2,3,4,5",
155 "PEBS": "1",
162 "Counter": "0,1,2,3,4,5,6,7",
165 "PEBS": "1",
172 …"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instruct…
173 "Counter": "0,1,2,3,4,5",
176 "PEBS": "1",
183 "Counter": "0,1,2,3,4,5,6,7",
186 "PEBS": "1",
193 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
194 "Counter": "0,1,2,3,4,5",
197 "PEBS": "1",
204 "Counter": "0,1,2,3,4,5",
205 "Deprecated": "1",
208 "PEBS": "1",
215 "Counter": "0,1,2,3,4,5",
216 "Deprecated": "1",
219 "PEBS": "1",
225 "BriefDescription": "Counts the number of near CALL branch instructions retired.",
226 "Counter": "0,1,2,3,4,5",
229 "PEBS": "1",
236 "Counter": "0,1,2,3,4,5,6,7",
239 "PEBS": "1",
246 "BriefDescription": "Counts the number of near RET branch instructions retired.",
247 "Counter": "0,1,2,3,4,5",
250 "PEBS": "1",
257 "Counter": "0,1,2,3,4,5,6,7",
260 "PEBS": "1",
267 "BriefDescription": "Counts the number of near taken branch instructions retired.",
268 "Counter": "0,1,2,3,4,5",
271 "PEBS": "1",
278 "Counter": "0,1,2,3,4,5,6,7",
281 "PEBS": "1",
289 "Counter": "0,1,2,3,4,5",
290 "Deprecated": "1",
293 "PEBS": "1",
299 "BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
300 "Counter": "0,1,2,3,4,5",
303 "PEBS": "1",
310 "Counter": "0,1,2,3,4,5",
311 "Deprecated": "1",
314 "PEBS": "1",
321 "Counter": "0,1,2,3,4,5",
322 "Deprecated": "1",
325 "PEBS": "1",
331 …"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all b…
332 "Counter": "0,1,2,3,4,5",
335 "PEBS": "1",
336 …of mispredicted branch instructions retired. All branch type instructions are accounted for. Pre…
342 "Counter": "0,1,2,3,4,5,6,7",
345 "PEBS": "1",
346 …sprediction occurs when the processor incorrectly predicts the destination of the branch. When th…
351 …"BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instr…
352 "Counter": "0,1,2,3,4,5",
355 "PEBS": "1",
362 "Counter": "0,1,2,3,4,5,6,7",
365 "PEBS": "1",
372 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
373 "Counter": "0,1,2,3,4,5,6,7",
376 "PEBS": "1",
377 …"PublicDescription": "Counts the number of conditional branch instructions retired that were mispr…
383 …"BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch…
384 "Counter": "0,1,2,3,4,5",
387 "PEBS": "1",
393 … "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
394 "Counter": "0,1,2,3,4,5,6,7",
397 "PEBS": "1",
404 …"BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL br…
405 "Counter": "0,1,2,3,4,5",
408 "PEBS": "1",
414 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
415 "Counter": "0,1,2,3,4,5,6,7",
418 "PEBS": "1",
419 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
425 …"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions reti…
426 "Counter": "0,1,2,3,4,5",
429 "PEBS": "1",
436 "Counter": "0,1,2,3,4,5,6,7",
439 "PEBS": "1",
447 "Counter": "0,1,2,3,4,5",
448 "Deprecated": "1",
451 "PEBS": "1",
458 "Counter": "0,1,2,3,4,5",
459 "Deprecated": "1",
462 "PEBS": "1",
468 … "BriefDescription": "Counts the number of mispredicted near taken branch instructions retired.",
469 "Counter": "0,1,2,3,4,5",
472 "PEBS": "1",
478 …"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
479 "Counter": "0,1,2,3,4,5,6,7",
482 "PEBS": "1",
483 …"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and…
490 "Counter": "0,1,2,3,4,5",
491 "Deprecated": "1",
494 "PEBS": "1",
500 …"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PE…
501 "Counter": "0,1,2,3,4,5,6,7",
504 "PEBS": "1",
505 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
511 … "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
512 "Counter": "0,1,2,3,4,5",
515 "PEBS": "1",
522 "Counter": "0,1,2,3,4,5",
523 "Deprecated": "1",
526 "PEBS": "1",
532 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
533 "Counter": "0,1,2,3,4,5,6,7",
536 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
542 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
543 "Counter": "0,1,2,3,4,5,6,7",
546 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
552 …"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 A…
553 "Counter": "0,1,2,3,4,5,6,7",
556 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optim…
562 "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
563 "Counter": "Fixed counter 1",
565 …of core cycles while the core is not in a halt state. The core enters the halt state when it is ru…
571 "BriefDescription": "Counts the number of unhalted core clock cycles.",
572 "Counter": "0,1,2,3,4,5",
575 …"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The …
581 "Counter": "0,1,2,3,4,5,6,7",
591 "Counter": "0,1,2,3,4,5,6,7",
601 "Counter": "0,1,2,3,4,5,6,7",
610 "Counter": "0,1,2,3,4,5,6,7",
611 "CounterMask": "1",
612 "EdgeDetect": "1",
621 "Counter": "0,1,2,3,4,5,6,7",
624 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
630 …"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed…
633 …"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. …
642 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
648 … "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
649 "Counter": "0,1,2,3,4,5",
652 …"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. …
659 "Counter": "0,1,2,3,4,5,6,7",
662 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
668 "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
669 "Counter": "Fixed counter 1",
671 …of core cycles while the core is not in a halt state. The core enters the halt state when it is r…
678 "Counter": "Fixed counter 1",
680 …"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. Th…
686 "BriefDescription": "Counts the number of unhalted core clock cycles.",
687 "Counter": "0,1,2,3,4,5",
690 …"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The…
696 "Counter": "0,1,2,3,4,5,6,7",
699 …"PublicDescription": "This is an architectural event that counts the number of thread cycles while…
705 "Counter": "0,1,2,3",
715 "Counter": "0,1,2,3",
716 "CounterMask": "1",
725 "Counter": "0,1,2,3,4,5,6,7",
735 "Counter": "0,1,2,3",
745 "Counter": "0,1,2,3",
755 "Counter": "0,1,2,3,4,5,6,7",
756 "CounterMask": "4",
764 …"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was no…
765 "Counter": "0,1,2,3,4,5,6,7",
767 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
768 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
774 …"BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station…
775 "Counter": "0,1,2,3,4,5,6,7",
783 …"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was …
784 "Counter": "0,1,2,3,4,5,6,7",
787 …"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and …
793 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
794 "Counter": "0,1,2,3,4,5,6,7",
797 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
803 …"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was …
804 "Counter": "0,1,2,3,4,5,6,7",
806 "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
807 …"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS…
814 "Counter": "0,1,2,3,4,5,6,7",
824 "Counter": "0,1,2,3,4,5,6,7",
835 "Counter": "0,1,2,3,4,5,6,7",
838 …"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station …
845 "Counter": "0,1,2,3",
848 …"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline…
854 "BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
857 "PEBS": "1",
858 …otal number of instructions that retired. For instructions that consist of multiple uops, this eve…
864 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
867 "PEBS": "1",
868 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
874 "BriefDescription": "Counts the total number of instructions retired.",
875 "Counter": "0,1,2,3,4,5",
878 "PEBS": "1",
879 …otal number of instructions that retired. For instructions that consist of multiple uops, this eve…
884 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
885 "Counter": "0,1,2,3,4,5,6,7",
888 "PEBS": "1",
889 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
895 "Counter": "0,1,2,3,4,5,6,7",
898 "PEBS": "1",
905 "Counter": "0,1,2,3,4,5,6,7",
908 "PEBS": "1",
915 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
918 "PEBS": "1",
919 … version of INST_RETIRED that allows for a precise distribution of samples across instructions ret…
925 "BriefDescription": "Iterations of Repeat string retired instructions.",
926 "Counter": "0,1,2,3,4,5,6,7",
929 "PEBS": "1",
930 …of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a…
937 "Counter": "0,1,2,3,4,5,6,7",
938 "CounterMask": "1",
939 "EdgeDetect": "1",
942 …"PublicDescription": "Counts the number of speculative clears due to any type of branch mispredict…
949 "Counter": "0,1,2,3,4,5,6,7",
959 "Counter": "0,1,2,3,4,5,6,7",
968 "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).",
969 "Counter": "0,1,2,3,4,5,6,7",
980 "Counter": "0,1,2,3,4,5,6,7",
983 …ublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped…
990 "Counter": "0,1,2,3,4,5,6,7",
999 "Counter": "0,1,2,3,4,5,6,7",
1007 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
1008 "Counter": "0,1,2,3,4,5,6,7",
1011 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
1017 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
1018 "Counter": "0,1,2,3,4,5,6,7",
1021 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
1028 "Counter": "0,1,2,3,4,5,6,7",
1037 "Counter": "0,1,2,3,4,5,6,7",
1046 "Counter": "0,1,2,3,4,5,6,7",
1055 "Counter": "0,1,2,3,4,5,6,7",
1064 "Counter": "0,1,2,3,4,5",
1065 "Deprecated": "1",
1067 "EventName": "LD_BLOCKS.4K_ALIAS",
1068 "PEBS": "1",
1074 …er of retired loads that are blocked because it initially appears to be store forward blocked, but…
1075 "Counter": "0,1,2,3,4,5",
1078 "PEBS": "1",
1085 "Counter": "0,1,2,3",
1088 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in M…
1094 …"BriefDescription": "Counts the number of retired loads that are blocked because its address exact…
1095 "Counter": "0,1,2,3,4,5",
1098 "PEBS": "1",
1104 …"BriefDescription": "The number of times that split load operations are temporarily blocked becaus…
1105 "Counter": "0,1,2,3",
1108 …"PublicDescription": "Counts the number of times that split load operations are temporarily blocke…
1115 "Counter": "0,1,2,3",
1118 …of times where store forwarding was prevented for a load operation. The most common case is a load…
1124 …"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) all…
1125 "Counter": "0,1,2,3",
1128 …-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It ca…
1135 "Counter": "0,1,2,3,4,5,6,7",
1136 "CounterMask": "1",
1139 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
1145 …"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the…
1146 "Counter": "0,1,2,3,4,5,6,7",
1150 …blicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-str…
1156 "BriefDescription": "Number of Uops delivered by the LSD.",
1157 "Counter": "0,1,2,3,4,5,6,7",
1160 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
1166 "BriefDescription": "Number of machine clears (nukes) of any type.",
1167 "Counter": "0,1,2,3,4,5,6,7",
1168 "CounterMask": "1",
1169 "EdgeDetect": "1",
1172 "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
1178 …"BriefDescription": "Counts the number of machine clears due to memory ordering in which an intern…
1179 "Counter": "0,1,2,3,4,5",
1187 "BriefDescription": "Counts the number of machines clears due to memory renaming.",
1188 "Counter": "0,1,2,3,4,5",
1196 …"BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side …
1197 "Counter": "0,1,2,3,4,5",
1205 …iefDescription": "Counts the number of machine clears that flush the pipeline and restart the mach…
1206 "Counter": "0,1,2,3,4,5",
1214 …efDescription": "Counts the number of machine clears due to program modifying data (self modifying…
1215 "Counter": "0,1,2,3,4,5",
1223 "BriefDescription": "Self-modifying code (SMC) detected.",
1224 "Counter": "0,1,2,3,4,5,6,7",
1227 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
1234 "Counter": "0,1,2,3,4,5,6,7",
1237 "PublicDescription": "number of LFENCE retired instructions",
1243 …"BriefDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA3…
1244 "Counter": "0,1,2,3,4,5",
1247 "PEBS": "1",
1248 …"PublicDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA…
1255 "Counter": "0,1,2,3,4,5,6,7",
1258 …d to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stac…
1265 "Counter": "0,1,2,3,4,5,6,7",
1268 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
1275 "Counter": "0,1,2,3,4,5,6,7",
1283 …": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) sco…
1284 "Counter": "0,1,2,3,4,5",
1287 …": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) sco…
1293 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
1294 "Counter": "0,1,2,3,4,5,6,7",
1297 …n": "Number of slots in TMA method where no micro-operations were being issued from front-end to b…
1307 …on": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all t…
1317 …of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions.…
1324 "Counter": "0,1,2,3,4,5,6,7",
1332 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
1335 …of available slots for an unhalted logical processor. The event increments by machine-width of the…
1341 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
1342 "Counter": "0,1,2,3,4,5,6,7",
1345 …of available slots for an unhalted logical processor. The event increments by machine-width of the…
1351 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend …
1352 "Counter": "0,1,2,3,4,5",
1355 …"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend…
1360 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
1361 "Counter": "0,1,2,3,4,5",
1369 …s the total number of issue slots that were not consumed by the backend because allocation is stal…
1370 "Counter": "0,1,2,3,4,5",
1378 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
1379 "Counter": "0,1,2,3,4,5",
1387 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
1388 "Counter": "0,1,2,3,4,5",
1396 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by …
1397 "Counter": "0,1,2,3,4,5",
1404 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
1405 "Counter": "0,1,2,3,4,5",
1413 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
1414 "Counter": "0,1,2,3,4,5",
1422 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
1423 "Counter": "0,1,2,3,4,5",
1431 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
1432 "Counter": "0,1,2,3,4,5",
1440 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
1441 "Counter": "0,1,2,3,4,5",
1449 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
1450 "Counter": "0,1,2,3,4,5",
1458 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by …
1459 "Counter": "0,1,2,3,4,5",
1466 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
1467 "Counter": "0,1,2,3,4,5",
1470 …"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the …
1476 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
1477 "Counter": "0,1,2,3,4,5",
1480 …"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the …
1486 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
1487 "Counter": "0,1,2,3,4,5",
1495 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
1496 "Counter": "0,1,2,3,4,5",
1504 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
1505 "Counter": "0,1,2,3,4,5",
1513 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
1514 "Counter": "0,1,2,3,4,5",
1522 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
1523 "Counter": "0,1,2,3,4,5",
1526 …"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the …
1532 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
1533 "Counter": "0,1,2,3,4,5",
1541 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
1542 "Counter": "0,1,2,3,4,5",
1550 "BriefDescription": "Counts the total number of consumed retirement slots.",
1551 "Counter": "0,1,2,3,4,5",
1554 "PEBS": "1",
1560 "Counter": "0,1,2,3",
1569 "Counter": "0,1,2,3,4,5,6,7",
1572 "PublicDescription": "Number of uops dispatch to execution port 0.",
1578 "BriefDescription": "Uops executed on port 1",
1579 "Counter": "0,1,2,3,4,5,6,7",
1582 "PublicDescription": "Number of uops dispatch to execution port 1.",
1589 "Counter": "0,1,2,3,4,5,6,7",
1592 "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
1598 "BriefDescription": "Uops executed on ports 4 and 9",
1599 "Counter": "0,1,2,3,4,5,6,7",
1602 "PublicDescription": "Number of uops dispatch to execution ports 4 and 9",
1609 "Counter": "0,1,2,3,4,5,6,7",
1612 "PublicDescription": "Number of uops dispatch to execution ports 5 and 11",
1619 "Counter": "0,1,2,3,4,5,6,7",
1622 "PublicDescription": "Number of uops dispatch to execution port 6.",
1629 "Counter": "0,1,2,3,4,5,6,7",
1632 "PublicDescription": "Number of uops dispatch to execution ports 7 and 8.",
1638 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1639 "Counter": "0,1,2,3,4,5,6,7",
1640 "CounterMask": "1",
1643 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
1649 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1650 "Counter": "0,1,2,3,4,5,6,7",
1654 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
1660 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1661 "Counter": "0,1,2,3,4,5,6,7",
1665 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
1671 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1672 "Counter": "0,1,2,3,4,5,6,7",
1673 "CounterMask": "4",
1676 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1682 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1683 "Counter": "0,1,2,3,4,5,6,7",
1684 "CounterMask": "1",
1687 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1693 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1694 "Counter": "0,1,2,3,4,5,6,7",
1698 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1704 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1705 "Counter": "0,1,2,3,4,5,6,7",
1709 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1715 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1716 "Counter": "0,1,2,3,4,5,6,7",
1717 "CounterMask": "4",
1720 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1726 …"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread…
1727 "Counter": "0,1,2,3,4,5,6,7",
1728 "CounterMask": "1",
1731 "Invert": "1",
1739 "Counter": "0,1,2,3,4,5,6,7",
1740 "CounterMask": "1",
1741 "Deprecated": "1",
1744 "Invert": "1",
1750 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1751 "Counter": "0,1,2,3,4,5,6,7",
1759 "BriefDescription": "Counts the number of x87 uops dispatched.",
1760 "Counter": "0,1,2,3,4,5,6,7",
1763 "PublicDescription": "Counts the number of x87 uops executed.",
1769 "BriefDescription": "Counts the number of uops issued by the front end every cycle.",
1770 "Counter": "0,1,2,3,4,5",
1773 …of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are deliver…
1779 "Counter": "0,1,2,3,4,5,6,7",
1782 …"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to…
1789 "Counter": "0,1,2,3,4,5,6,7",
1790 "CounterMask": "1",
1798 "BriefDescription": "Counts the total number of uops retired.",
1799 "Counter": "0,1,2,3,4,5",
1802 "PEBS": "1",
1808 "Counter": "0,1,2,3,4,5,6,7",
1809 "CounterMask": "1",
1818 "BriefDescription": "Retired uops except the last uop of each instruction.",
1819 "Counter": "0,1,2,3,4,5,6,7",
1822 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1828 "BriefDescription": "Counts the number of integer divide uops retired.",
1829 "Counter": "0,1,2,3,4,5",
1832 "PEBS": "1",
1838 …"BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-seq…
1839 "Counter": "0,1,2,3,4,5",
1842 "PEBS": "1",
1843 …"PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcod…
1850 "Counter": "0,1,2,3,4,5,6,7",
1861 "Counter": "0,1,2,3,4,5,6,7",
1871 "Counter": "0,1,2,3,4,5,6,7",
1872 "CounterMask": "1",
1875 "Invert": "1",
1883 "Counter": "0,1,2,3,4,5,6,7",
1884 "CounterMask": "1",
1885 "Deprecated": "1",
1888 "Invert": "1",
1894 "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.",
1895 "Counter": "0,1,2,3,4,5",
1898 "PEBS": "1",