Lines Matching +full:1 +full:- +full:of +full:- +full:4
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PEBS": "1",
32 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBS": "1",
42 "Counter": "0,1,2,3,4,5,6,7",
45 "PEBS": "1",
52 "Counter": "0,1,2,3,4,5,6,7",
55 "PEBS": "1",
62 "Counter": "0,1,2,3,4,5,6,7",
65 "PEBS": "1",
72 "Counter": "0,1,2,3,4,5,6,7",
75 "PEBS": "1",
82 "Counter": "0,1,2,3,4,5,6,7",
85 "PEBS": "1",
92 "Counter": "0,1,2,3,4,5,6,7",
95 "PEBS": "1",
102 "Counter": "0,1,2,3,4,5,6,7",
105 "PEBS": "1",
112 "Counter": "0,1,2,3,4,5,6,7",
115 "PEBS": "1",
116 …sprediction occurs when the processor incorrectly predicts the destination of the branch. When th…
121 "Counter": "0,1,2,3,4,5,6,7",
124 "PEBS": "1",
130 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
131 "Counter": "0,1,2,3,4,5,6,7",
134 "PEBS": "1",
135 …"PublicDescription": "Counts the number of conditional branch instructions retired that were mispr…
140 … "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
141 "Counter": "0,1,2,3,4,5,6,7",
144 "PEBS": "1",
150 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
151 "Counter": "0,1,2,3,4,5,6,7",
154 "PEBS": "1",
155 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
161 "Counter": "0,1,2,3,4,5,6,7",
164 "PEBS": "1",
170 …"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
171 "Counter": "0,1,2,3,4,5,6,7",
174 "PEBS": "1",
175 …"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and…
180 …"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PE…
181 "Counter": "0,1,2,3,4,5,6,7",
184 "PEBS": "1",
185 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
191 "Counter": "0,1,2,3,4,5,6,7",
200 "Counter": "0,1,2,3,4,5,6,7",
209 "Counter": "0,1,2,3,4,5,6,7",
212 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
220 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
226 "Counter": "0,1,2,3,4,5,6,7",
235 "Counter": "Fixed counter 1",
237 …"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. Th…
243 "Counter": "0,1,2,3,4,5,6,7",
246 …"PublicDescription": "This is an architectural event that counts the number of thread cycles while…
251 "Counter": "0,1,2,3",
260 "Counter": "0,1,2,3",
261 "CounterMask": "1",
269 "Counter": "0,1,2,3,4,5,6,7",
278 "Counter": "0,1,2,3",
287 "Counter": "0,1,2,3",
296 "Counter": "0,1,2,3,4,5,6,7",
305 "Counter": "0,1,2,3,4,5,6,7",
306 "CounterMask": "4",
313 …"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was no…
314 "Counter": "0,1,2,3,4,5,6,7",
316 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
317 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
322 …"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was …
323 "Counter": "0,1,2,3,4,5,6,7",
326 …"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and …
331 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
332 "Counter": "0,1,2,3,4,5,6,7",
335 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
340 …"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was …
341 "Counter": "0,1,2,3,4,5,6,7",
343 "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
344 …"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS…
349 …": "Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle…
350 "Counter": "0,1,2,3,4,5,6,7",
354 …nts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle…
360 "Counter": "0,1,2,3,4,5,6,7",
370 "Counter": "0,1,2,3,4,5,6,7",
373 …"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station …
378 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al…
379 "Counter": "0,1,2,3",
382 …of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instructi…
388 "Counter": "0,1,2,3",
391 …"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline…
396 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
399 "PEBS": "1",
400 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
405 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
406 "Counter": "0,1,2,3,4,5,6,7",
409 "PEBS": "1",
410 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
415 "Counter": "0,1,2,3,4,5,6,7",
418 "PEBS": "1",
424 …"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP …
427 "PEBS": "1",
428 …rsion of INST_RETIRED that allows for a more unbiased distribution of samples across instructions …
433 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
434 "Counter": "0,1,2,3,4,5,6,7",
435 "CounterMask": "1",
438 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
444 "Counter": "0,1,2,3,4,5,6,7",
445 "CounterMask": "1",
446 "EdgeDetect": "1",
449 …"PublicDescription": "Counts the number of speculative clears due to any type of branch mispredict…
455 "Counter": "0,1,2,3,4,5,6,7",
464 "Counter": "0,1,2,3,4,5,6,7",
473 "Counter": "0,1,2,3,4,5,6,7",
476 …ublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped…
481 …"BriefDescription": "The number of times that split load operations are temporarily blocked becaus…
482 "Counter": "0,1,2,3",
485 …"PublicDescription": "Counts the number of times that split load operations are temporarily blocke…
491 "Counter": "0,1,2,3",
494 …of times where store forwarding was prevented for a load operation. The most common case is a load…
500 "Counter": "0,1,2,3",
503 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in M…
508 …"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) all…
509 "Counter": "0,1,2,3",
512 …-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It ca…
518 "Counter": "0,1,2,3",
519 "CounterMask": "1",
522 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
527 …"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the…
528 "Counter": "0,1,2,3",
532 …blicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-str…
537 "BriefDescription": "Number of Uops delivered by the LSD.",
538 "Counter": "0,1,2,3",
541 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
546 "BriefDescription": "Number of machine clears (nukes) of any type.",
547 "Counter": "0,1,2,3,4,5,6,7",
548 "CounterMask": "1",
549 "EdgeDetect": "1",
552 "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
557 "BriefDescription": "Self-modifying code (SMC) detected.",
558 "Counter": "0,1,2,3,4,5,6,7",
561 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
567 "Counter": "0,1,2,3,4,5,6,7",
570 …d to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stac…
575 …"BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SK…
576 "Counter": "0,1,2,3,4,5,6,7",
579 …"PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on …
585 "Counter": "0,1,2,3,4,5,6,7",
588 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
594 "Counter": "0,1,2,3,4,5,6,7",
602 "Counter": "0,1,2,3,4,5,6,7",
605 … This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch misp…
610 "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
611 "Counter": "0,1,2,3,4,5,6,7",
612 "CounterMask": "1",
613 "EdgeDetect": "1",
616 "Invert": "1",
617 …of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on fron…
622 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
623 "Counter": "0,1,2,3,4,5,6,7",
626 …of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being …
631 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
634 …of available slots for an unhalted logical processor. The event increments by machine-width of the…
639 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
640 "Counter": "0,1,2,3,4,5,6,7",
643 …of available slots for an unhalted logical processor. The event increments by machine-width of the…
648 … "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
649 "Counter": "0,1,2,3",
657 "BriefDescription": "Number of uops executed on port 0",
658 "Counter": "0,1,2,3,4,5,6,7",
661 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
666 "BriefDescription": "Number of uops executed on port 1",
667 "Counter": "0,1,2,3,4,5,6,7",
670 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
675 "BriefDescription": "Number of uops executed on port 2 and 3",
676 "Counter": "0,1,2,3,4,5,6,7",
679 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
684 "BriefDescription": "Number of uops executed on port 4 and 9",
685 "Counter": "0,1,2,3,4,5,6,7",
688 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
693 "BriefDescription": "Number of uops executed on port 5",
694 "Counter": "0,1,2,3,4,5,6,7",
697 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
702 "BriefDescription": "Number of uops executed on port 6",
703 "Counter": "0,1,2,3,4,5,6,7",
706 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
711 "BriefDescription": "Number of uops executed on port 7 and 8",
712 "Counter": "0,1,2,3,4,5,6,7",
715 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
720 "BriefDescription": "Number of uops executed on the core.",
721 "Counter": "0,1,2,3,4,5,6,7",
724 "PublicDescription": "Counts the number of uops executed from any thread.",
729 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
730 "Counter": "0,1,2,3,4,5,6,7",
731 "CounterMask": "1",
734 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
739 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
740 "Counter": "0,1,2,3,4,5,6,7",
744 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
749 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
750 "Counter": "0,1,2,3,4,5,6,7",
754 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
759 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
760 "Counter": "0,1,2,3,4,5,6,7",
761 "CounterMask": "4",
764 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
769 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
770 "Counter": "0,1,2,3,4,5,6,7",
771 "CounterMask": "1",
774 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
779 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
780 "Counter": "0,1,2,3,4,5,6,7",
784 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
789 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
790 "Counter": "0,1,2,3,4,5,6,7",
794 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
799 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
800 "Counter": "0,1,2,3,4,5,6,7",
801 "CounterMask": "4",
804 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
809 …"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread…
810 "Counter": "0,1,2,3,4,5,6,7",
811 "CounterMask": "1",
814 "Invert": "1",
820 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
821 "Counter": "0,1,2,3,4,5,6,7",
828 "BriefDescription": "Counts the number of x87 uops dispatched.",
829 "Counter": "0,1,2,3,4,5,6,7",
832 "PublicDescription": "Counts the number of x87 uops executed.",
838 "Counter": "0,1,2,3,4,5,6,7",
841 …"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to…
847 "Counter": "0,1,2,3,4,5,6,7",
848 "CounterMask": "1",
851 "Invert": "1",
857 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
858 "Counter": "0,1,2,3,4,5,6,7",
861 …of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in ord…
867 "Counter": "0,1,2,3,4,5,6,7",
876 "Counter": "0,1,2,3,4,5,6,7",
877 "CounterMask": "1",
880 "Invert": "1",
887 "Counter": "0,1,2,3,4,5,6,7",
891 "Invert": "1",
892 …"PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) appl…