Lines Matching +full:1 +full:- +full:of +full:- +full:4
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PEBS": "1",
32 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBS": "1",
42 "Counter": "0,1,2,3,4,5,6,7",
45 "PEBS": "1",
52 "Counter": "0,1,2,3,4,5,6,7",
55 "PEBS": "1",
62 "Counter": "0,1,2,3,4,5,6,7",
65 "PEBS": "1",
72 "Counter": "0,1,2,3,4,5,6,7",
75 "PEBS": "1",
82 "Counter": "0,1,2,3,4,5,6,7",
85 "PEBS": "1",
92 "Counter": "0,1,2,3,4,5,6,7",
95 "PEBS": "1",
102 "Counter": "0,1,2,3,4,5,6,7",
105 "PEBS": "1",
112 "Counter": "0,1,2,3,4,5,6,7",
115 "PEBS": "1",
116 …sprediction occurs when the processor incorrectly predicts the destination of the branch. When th…
121 "Counter": "0,1,2,3,4,5,6,7",
124 "PEBS": "1",
130 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
131 "Counter": "0,1,2,3,4,5,6,7",
134 "PEBS": "1",
135 …"PublicDescription": "Counts the number of conditional branch instructions retired that were mispr…
140 … "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
141 "Counter": "0,1,2,3,4,5,6,7",
144 "PEBS": "1",
150 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
151 "Counter": "0,1,2,3,4,5,6,7",
154 "PEBS": "1",
155 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
161 "Counter": "0,1,2,3,4,5,6,7",
164 "PEBS": "1",
170 …"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
171 "Counter": "0,1,2,3,4,5,6,7",
174 "PEBS": "1",
175 …"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and…
180 …"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PE…
181 "Counter": "0,1,2,3,4,5,6,7",
184 "PEBS": "1",
185 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
191 "Counter": "0,1,2,3,4,5,6,7",
200 "Counter": "0,1,2,3,4,5,6,7",
209 "Counter": "0,1,2,3,4,5,6,7",
212 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
220 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
226 "Counter": "0,1,2,3,4,5,6,7",
235 "Counter": "Fixed counter 1",
237 …"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. Th…
243 "Counter": "0,1,2,3,4,5,6,7",
246 …"PublicDescription": "This is an architectural event that counts the number of thread cycles while…
251 "Counter": "0,1,2,3",
260 "Counter": "0,1,2,3",
261 "CounterMask": "1",
269 "Counter": "0,1,2,3,4,5,6,7",
278 "Counter": "0,1,2,3",
287 "Counter": "0,1,2,3",
296 "Counter": "0,1,2,3,4,5,6,7",
305 "Counter": "0,1,2,3,4,5,6,7",
306 "CounterMask": "4",
313 …"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was no…
314 "Counter": "0,1,2,3,4,5,6,7",
316 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
317 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
322 …"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was …
323 "Counter": "0,1,2,3,4,5,6,7",
326 …"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and …
331 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
332 "Counter": "0,1,2,3,4,5,6,7",
335 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
340 …"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was …
341 "Counter": "0,1,2,3,4,5,6,7",
343 "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
344 …"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS…
350 "Counter": "0,1,2,3,4,5,6,7",
359 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al…
360 "Counter": "0,1,2,3",
363 …of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instructi…
369 "Counter": "0,1,2,3",
372 …"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline…
377 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
380 "PEBS": "1",
381 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
386 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
387 "Counter": "0,1,2,3,4,5,6,7",
390 "PEBS": "1",
391 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
395 "BriefDescription": "Number of all retired NOP instructions.",
396 "Counter": "0,1,2,3,4,5,6,7",
399 "PEBS": "1",
404 …"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP …
407 "PEBS": "1",
408 …rsion of INST_RETIRED that allows for a more unbiased distribution of samples across instructions …
413 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
414 "Counter": "0,1,2,3,4,5,6,7",
415 "CounterMask": "1",
418 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
424 "Counter": "0,1,2,3,4,5,6,7",
425 "CounterMask": "1",
426 "EdgeDetect": "1",
429 …"PublicDescription": "Counts the number of speculative clears due to any type of branch mispredict…
435 "Counter": "0,1,2,3,4,5,6,7",
444 "Counter": "0,1,2,3,4,5,6,7",
453 "Counter": "0,1,2,3,4,5,6,7",
456 …ublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped…
461 …"BriefDescription": "The number of times that split load operations are temporarily blocked becaus…
462 "Counter": "0,1,2,3",
465 …"PublicDescription": "Counts the number of times that split load operations are temporarily blocke…
471 "Counter": "0,1,2,3",
474 …of times where store forwarding was prevented for a load operation. The most common case is a load…
480 "Counter": "0,1,2,3",
483 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies due …
488 …"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) all…
489 "Counter": "0,1,2,3",
492 …-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It ca…
498 "Counter": "0,1,2,3",
499 "CounterMask": "1",
502 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
507 …"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the…
508 "Counter": "0,1,2,3",
512 …blicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-str…
517 "BriefDescription": "Number of Uops delivered by the LSD.",
518 "Counter": "0,1,2,3",
521 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
526 "BriefDescription": "Number of machine clears (nukes) of any type.",
527 "Counter": "0,1,2,3,4,5,6,7",
528 "CounterMask": "1",
529 "EdgeDetect": "1",
532 "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
537 "BriefDescription": "Self-modifying code (SMC) detected.",
538 "Counter": "0,1,2,3,4,5,6,7",
541 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
547 "Counter": "0,1,2,3,4,5,6,7",
550 …d to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stac…
555 …"BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SK…
556 "Counter": "0,1,2,3,4,5,6,7",
559 …"PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on …
565 "Counter": "0,1,2,3,4,5,6,7",
568 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
574 "Counter": "0,1,2,3,4,5,6,7",
582 "Counter": "0,1,2,3,4,5,6,7",
585 … This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch misp…
590 "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
591 "Counter": "0,1,2,3,4,5,6,7",
592 "CounterMask": "1",
593 "EdgeDetect": "1",
596 "Invert": "1",
597 …of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on fron…
602 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
603 "Counter": "0,1,2,3,4,5,6,7",
606 …of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being …
611 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
614 …of available slots for an unhalted logical processor. The event increments by machine-width of the…
619 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
620 "Counter": "0,1,2,3,4,5,6,7",
623 …of available slots for an unhalted logical processor. The event increments by machine-width of the…
628 … "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
629 "Counter": "0,1,2,3",
637 "BriefDescription": "Number of uops executed on port 0",
638 "Counter": "0,1,2,3,4,5,6,7",
641 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
646 "BriefDescription": "Number of uops executed on port 1",
647 "Counter": "0,1,2,3,4,5,6,7",
650 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
655 "BriefDescription": "Number of uops executed on port 2 and 3",
656 "Counter": "0,1,2,3,4,5,6,7",
659 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
664 "BriefDescription": "Number of uops executed on port 4 and 9",
665 "Counter": "0,1,2,3,4,5,6,7",
668 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
673 "BriefDescription": "Number of uops executed on port 5",
674 "Counter": "0,1,2,3,4,5,6,7",
677 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
682 "BriefDescription": "Number of uops executed on port 6",
683 "Counter": "0,1,2,3,4,5,6,7",
686 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
691 "BriefDescription": "Number of uops executed on port 7 and 8",
692 "Counter": "0,1,2,3,4,5,6,7",
695 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
700 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
701 "Counter": "0,1,2,3,4,5,6,7",
702 "CounterMask": "1",
705 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
710 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
711 "Counter": "0,1,2,3,4,5,6,7",
715 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
720 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
721 "Counter": "0,1,2,3,4,5,6,7",
725 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
730 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
731 "Counter": "0,1,2,3,4,5,6,7",
732 "CounterMask": "4",
735 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
740 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
741 "Counter": "0,1,2,3,4,5,6,7",
742 "CounterMask": "1",
745 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
750 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
751 "Counter": "0,1,2,3,4,5,6,7",
755 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
760 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
761 "Counter": "0,1,2,3,4,5,6,7",
765 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
770 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
771 "Counter": "0,1,2,3,4,5,6,7",
772 "CounterMask": "4",
775 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
780 …"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread…
781 "Counter": "0,1,2,3,4,5,6,7",
782 "CounterMask": "1",
785 "Invert": "1",
791 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
792 "Counter": "0,1,2,3,4,5,6,7",
799 "BriefDescription": "Counts the number of x87 uops dispatched.",
800 "Counter": "0,1,2,3,4,5,6,7",
803 "PublicDescription": "Counts the number of x87 uops executed.",
809 "Counter": "0,1,2,3,4,5,6,7",
812 …"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to…
818 "Counter": "0,1,2,3,4,5,6,7",
819 "CounterMask": "1",
822 "Invert": "1",
828 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
829 "Counter": "0,1,2,3,4,5,6,7",
832 …of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in ord…
838 "Counter": "0,1,2,3,4,5,6,7",
847 "Counter": "0,1,2,3,4,5,6,7",
848 "CounterMask": "1",
851 "Invert": "1",
858 "Counter": "0,1,2,3,4,5,6,7",
862 "Invert": "1",
863 …"PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) appl…