include/variant/tie.h

6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
10  * Copyright (C) 1999-2007 Tensilica Inc.
16 #define XCHAL_CP_NUM			1	/* number of coprocessors */
17 #define XCHAL_CP_MAX			8	/* max CP ID + 1 (0 if none) */
18 #define XCHAL_CP_MASK			0x80	/* bitmask of all CPs by ID */
19 #define XCHAL_CP_PORT_MASK		0x80	/* bitmask of only port CPs */
21 /*  Basic parameters of each coprocessor:  */
24 #define XCHAL_CP7_SA_SIZE		0	/* size of state save area */
25 #define XCHAL_CP7_SA_ALIGN		1	/* min alignment of save area */
30 #define XCHAL_CP0_SA_ALIGN		1
32 #define XCHAL_CP1_SA_ALIGN		1
34 #define XCHAL_CP2_SA_ALIGN		1
36 #define XCHAL_CP3_SA_ALIGN		1
38 #define XCHAL_CP4_SA_ALIGN		1
40 #define XCHAL_CP5_SA_ALIGN		1
42 #define XCHAL_CP6_SA_ALIGN		1
44 /*  Save area for non-coprocessor optional and custom (TIE) state:  */
46 #define XCHAL_NCP_SA_ALIGN		4
49 #define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
50 #define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
53  * Detailed contents of save areas.
62  *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
63  *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
64  *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
66  *	galign = group byte alignment (power of 2) (galign >= align)
67  *	align = register byte alignment (power of 2)
70  *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
72  *	regnum = reg index in regfile, or special/TIE-user reg number
73  *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
75  *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
79  *  To filter out certain registers, e.g. to expand only the non-global
94  XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
95  XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
96  XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
97  XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
98  XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
99  XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
100  XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
101  XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0)
127 /* Byte length of instruction from its first nibble (op0 field), per FLIX.  */