Lines Matching +full:1 +full:- +full:of +full:- +full:4
3 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o…
4 "Counter": "0,1,2,3,4,5,6,7",
7 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C…
12 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on…
13 "Counter": "0,1,2,3,4,5,6,7",
16 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca…
21 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instr…
22 "Counter": "0,1,2,3,4,5,6,7",
29 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o…
30 "Counter": "0,1,2,3,4,5,6,7",
33 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache …
38 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icach…
39 "Counter": "0,1,2,3,4,5,6,7",
46 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icach…
47 "Counter": "0,1,2,3,4,5,6,7",
54 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 de…
55 "Counter": "0,1,2,3,4,5,6,7",
62 …"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hi…
63 "Counter": "0,1,2,3,4,5,6,7",
66 …"PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit…
71 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand…
72 "Counter": "0,1,2,3,4,5,6,7",
79 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand…
80 "Counter": "0,1,2,3,4,5,6,7",
87 …"BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM",
88 "Counter": "0,1,2,3,4,5,6,7",
95 "BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.",
96 "Counter": "0,1,2,3,4,5,6,7",
103 "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.",
104 "Counter": "0,1,2,3,4,5,6,7",
111 "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.",
112 "Counter": "0,1,2,3,4,5,6,7",
119 "BriefDescription": "Counts the number of load ops retired that miss in the L2 cache.",
120 "Counter": "0,1,2,3,4,5,6,7",
127 "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.",
128 "Counter": "0,1,2,3,4,5,6,7",
135 …"BriefDescription": "Counts the number of loads that hit in a write combining buffer (WCB), exclud…
136 "Counter": "0,1,2,3,4,5,6,7",
143 …"BriefDescription": "Counts the number of cycles that uops are blocked for any of the following re…
144 "Counter": "0,1,2,3,4,5,6,7",
151 …"BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full c…
152 "Counter": "0,1,2,3,4,5,6,7",
159 …"BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full conditio…
160 "Counter": "0,1,2,3,4,5,6,7",
167 …"BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full …
168 "Counter": "0,1,2,3,4,5,6,7",
175 "BriefDescription": "Counts the number of load ops retired.",
176 "Counter": "0,1,2,3,4,5,6,7",
177 "Data_LA": "1",
184 "BriefDescription": "Counts the number of store ops retired.",
185 "Counter": "0,1,2,3,4,5,6,7",
186 "Data_LA": "1",
193 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
194 "Counter": "0,1",
195 "Data_LA": "1",
204 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
205 "Counter": "0,1",
206 "Data_LA": "1",
215 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
216 "Counter": "0,1",
217 "Data_LA": "1",
226 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
227 "Counter": "0,1",
228 "Data_LA": "1",
237 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
238 "Counter": "0,1",
239 "Data_LA": "1",
248 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
249 "Counter": "0,1",
250 "Data_LA": "1",
259 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
260 "Counter": "0,1",
261 "Data_LA": "1",
270 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
271 "Counter": "0,1",
272 "Data_LA": "1",
281 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
282 "Counter": "0,1",
283 "Data_LA": "1",
292 …ion": "Counts the number of tagged load uops retired that exceed the latency threshold defined in …
293 "Counter": "0,1",
294 "Data_LA": "1",
303 … "BriefDescription": "Counts the number of load uops retired that performed one or more locks",
304 "Counter": "0,1,2,3,4,5,6,7",
305 "Data_LA": "1",
312 "BriefDescription": "Counts the number of memory uops retired that were splits.",
313 "Counter": "0,1,2,3,4,5,6,7",
314 "Data_LA": "1",
321 "BriefDescription": "Counts the number of retired split load uops.",
322 "Counter": "0,1,2,3,4,5,6,7",
323 "Data_LA": "1",
330 "BriefDescription": "Counts the number of retired split store uops.",
331 "Counter": "0,1,2,3,4,5,6,7",
332 "Data_LA": "1",
339 …"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES…
340 "Counter": "0,1,2,3,4,5,6,7",
341 "Data_LA": "1",
349 "Counter": "0,1,2,3,4,5,6,7",
358 …were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was for…
359 "Counter": "0,1,2,3,4,5,6,7",
369 "Counter": "0,1,2,3,4,5,6,7",
378 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…
379 "Counter": "0,1,2,3,4,5,6,7",