Lines Matching +full:1 +full:- +full:of +full:- +full:4
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
14 "Counter": "0,1,2,3,4,5,6,7",
15 "CounterMask": "1",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBS": "1",
41 "Counter": "0,1,2,3,4,5,6,7",
44 "PEBS": "1",
51 "Counter": "0,1,2,3,4,5,6,7",
54 "PEBS": "1",
61 "Counter": "0,1,2,3,4,5,6,7",
64 "PEBS": "1",
71 "Counter": "0,1,2,3,4,5,6,7",
74 "PEBS": "1",
81 "Counter": "0,1,2,3,4,5,6,7",
84 "PEBS": "1",
91 "Counter": "0,1,2,3,4,5,6,7",
94 "PEBS": "1",
101 "Counter": "0,1,2,3,4,5,6,7",
104 "PEBS": "1",
111 "Counter": "0,1,2,3,4,5,6,7",
114 "PEBS": "1",
121 "Counter": "0,1,2,3,4,5,6,7",
124 "PEBS": "1",
125 …sprediction occurs when the processor incorrectly predicts the destination of the branch. When th…
129 …ent may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on th…
130 "Counter": "0,1,2,3,4,5,6,7",
133 "PEBS": "1",
139 "Counter": "0,1,2,3,4,5,6,7",
142 "PEBS": "1",
148 …ent may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on th…
149 "Counter": "0,1,2,3,4,5,6,7",
152 "PEBS": "1",
157 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
158 "Counter": "0,1,2,3,4,5,6,7",
161 "PEBS": "1",
162 …"PublicDescription": "Counts the number of conditional branch instructions retired that were mispr…
167 …ed non-taken conditional branch instructions retired. This precise event may be used to get the mi…
168 "Counter": "0,1,2,3,4,5,6,7",
171 "PEBS": "1",
176 … "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
177 "Counter": "0,1,2,3,4,5,6,7",
180 "PEBS": "1",
186 …ent may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on th…
187 "Counter": "0,1,2,3,4,5,6,7",
190 "PEBS": "1",
195 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
196 "Counter": "0,1,2,3,4,5,6,7",
199 "PEBS": "1",
200 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
206 "Counter": "0,1,2,3,4,5,6,7",
209 "PEBS": "1",
215 …ent may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on th…
216 "Counter": "0,1,2,3,4,5,6,7",
219 "PEBS": "1",
224 …ent may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on th…
225 "Counter": "0,1,2,3,4,5,6,7",
228 "PEBS": "1",
233 …"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
234 "Counter": "0,1,2,3,4,5,6,7",
237 "PEBS": "1",
238 …"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and…
243 …ent may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on th…
244 "Counter": "0,1,2,3,4,5,6,7",
247 "PEBS": "1",
252 …"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PE…
253 "Counter": "0,1,2,3,4,5,6,7",
256 "PEBS": "1",
257 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
262 …ent may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on th…
263 "Counter": "0,1,2,3,4,5,6,7",
266 "PEBS": "1",
271 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
272 "Counter": "0,1,2,3,4,5,6,7",
275 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
280 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
281 "Counter": "0,1,2,3,4,5,6,7",
284 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
289 …"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 A…
290 "Counter": "0,1,2,3,4,5,6,7",
293 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optim…
299 "Counter": "0,1,2,3,4,5,6,7",
308 "Counter": "0,1,2,3,4,5,6,7",
317 "Counter": "0,1,2,3,4,5,6,7",
325 "Counter": "0,1,2,3,4,5,6,7",
326 "CounterMask": "1",
327 "EdgeDetect": "1",
335 "Counter": "0,1,2,3,4,5,6,7",
338 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
346 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
352 "Counter": "0,1,2,3,4,5,6,7",
355 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
361 "Counter": "Fixed counter 1",
363 …"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. Th…
369 "Counter": "0,1,2,3,4,5,6,7",
372 …"PublicDescription": "This is an architectural event that counts the number of thread cycles while…
377 "Counter": "0,1,2,3",
386 "Counter": "0,1,2,3",
387 "CounterMask": "1",
395 "Counter": "0,1,2,3,4,5,6,7",
404 "Counter": "0,1,2,3",
413 "Counter": "0,1,2,3",
422 "Counter": "0,1,2,3,4,5,6,7",
423 "CounterMask": "4",
430 …"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was no…
431 "Counter": "0,1,2,3,4,5,6,7",
433 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
434 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
439 …"BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station…
440 "Counter": "0,1,2,3,4,5,6,7",
447 …"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was …
448 "Counter": "0,1,2,3,4,5,6,7",
451 …"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and …
456 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
457 "Counter": "0,1,2,3,4,5,6,7",
460 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
465 …"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was …
466 "Counter": "0,1,2,3,4,5,6,7",
468 "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
469 …"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS…
475 "Counter": "0,1,2,3,4,5,6,7",
484 "Counter": "0,1,2,3,4,5,6,7",
494 "Counter": "0,1,2,3,4,5,6,7",
497 …"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station …
503 "Counter": "0,1,2,3",
506 …"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline…
511 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
514 "PEBS": "1",
515 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
520 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
521 "Counter": "0,1,2,3,4,5,6,7",
524 "PEBS": "1",
525 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
530 "Counter": "0,1,2,3,4,5,6,7",
533 "PEBS": "1",
539 "Counter": "0,1,2,3,4,5,6,7",
542 "PEBS": "1",
543 "PublicDescription": "Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions",
548 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
551 "PEBS": "1",
552 … version of INST_RETIRED that allows for a precise distribution of samples across instructions ret…
557 "BriefDescription": "Iterations of Repeat string retired instructions.",
558 "Counter": "0,1,2,3,4,5,6,7",
561 "PEBS": "1",
562 …of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a…
568 "Counter": "0,1,2,3,4,5,6,7",
569 "CounterMask": "1",
570 "EdgeDetect": "1",
573 …"PublicDescription": "Counts the number of speculative clears due to any type of branch mispredict…
579 "Counter": "0,1,2,3,4,5,6,7",
588 "Counter": "0,1,2,3,4,5,6,7",
596 "Counter": "0,1,2,3,4,5,6,7",
604 "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).",
605 "Counter": "0,1,2,3,4,5,6,7",
615 "Counter": "0,1,2,3,4,5,6,7",
618 …ublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped…
624 "Counter": "0,1,2,3,4,5,6,7",
632 "Counter": "0,1,2,3,4,5,6,7",
639 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
640 "Counter": "0,1,2,3,4,5,6,7",
643 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
648 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
649 "Counter": "0,1,2,3,4,5,6,7",
652 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
658 "Counter": "0,1,2,3,4,5,6,7",
666 "Counter": "0,1,2,3,4,5,6,7",
674 "Counter": "0,1,2,3,4,5,6,7",
682 "Counter": "0,1,2,3,4,5,6,7",
690 "Counter": "0,1,2,3",
693 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in M…
698 …"BriefDescription": "The number of times that split load operations are temporarily blocked becaus…
699 "Counter": "0,1,2,3",
702 …"PublicDescription": "Counts the number of times that split load operations are temporarily blocke…
708 "Counter": "0,1,2,3",
711 …of times where store forwarding was prevented for a load operation. The most common case is a load…
716 …"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) all…
717 "Counter": "0,1,2,3",
720 …-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It ca…
726 "Counter": "0,1,2,3,4,5,6,7",
727 "CounterMask": "1",
730 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
735 …"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the…
736 "Counter": "0,1,2,3,4,5,6,7",
740 …blicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-str…
745 "BriefDescription": "Number of Uops delivered by the LSD.",
746 "Counter": "0,1,2,3,4,5,6,7",
749 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
754 "BriefDescription": "Number of machine clears (nukes) of any type.",
755 "Counter": "0,1,2,3,4,5,6,7",
756 "CounterMask": "1",
757 "EdgeDetect": "1",
760 "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
765 "BriefDescription": "Self-modifying code (SMC) detected.",
766 "Counter": "0,1,2,3,4,5,6,7",
769 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
775 "Counter": "0,1,2,3,4,5,6,7",
778 "PublicDescription": "number of LFENCE retired instructions",
784 "Counter": "0,1,2,3,4,5,6,7",
787 …d to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stac…
793 "Counter": "0,1,2,3,4,5,6,7",
800 …unts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to la…
801 "Counter": "0,1,2,3,4,5,6,7",
804 …of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end…
813 …on": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all t…
822 …of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions.…
828 "Counter": "0,1,2,3,4,5,6,7",
835 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
838 …of available slots for an unhalted logical processor. The event increments by machine-width of the…
843 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
844 "Counter": "0,1,2,3,4,5,6,7",
847 …of available slots for an unhalted logical processor. The event increments by machine-width of the…
852 "BriefDescription": "Number of non dec-by-all uops decoded by decoder",
853 "Counter": "0,1,2,3",
856 … "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0.",
862 "Counter": "0,1,2,3,4,5,6,7",
865 "PublicDescription": "Number of uops dispatch to execution port 0.",
870 "BriefDescription": "Uops executed on port 1",
871 "Counter": "0,1,2,3,4,5,6,7",
874 "PublicDescription": "Number of uops dispatch to execution port 1.",
880 "Counter": "0,1,2,3,4,5,6,7",
883 "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
888 "BriefDescription": "Uops executed on ports 4 and 9",
889 "Counter": "0,1,2,3,4,5,6,7",
892 "PublicDescription": "Number of uops dispatch to execution ports 4 and 9",
898 "Counter": "0,1,2,3,4,5,6,7",
901 "PublicDescription": "Number of uops dispatch to execution ports 5 and 11",
907 "Counter": "0,1,2,3,4,5,6,7",
910 "PublicDescription": "Number of uops dispatch to execution port 6.",
916 "Counter": "0,1,2,3,4,5,6,7",
919 "PublicDescription": "Number of uops dispatch to execution ports 7 and 8.",
924 "BriefDescription": "Number of uops executed on the core.",
925 "Counter": "0,1,2,3,4,5,6,7",
928 "PublicDescription": "Counts the number of uops executed from any thread.",
933 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
934 "Counter": "0,1,2,3,4,5,6,7",
935 "CounterMask": "1",
938 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
943 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
944 "Counter": "0,1,2,3,4,5,6,7",
948 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
953 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
954 "Counter": "0,1,2,3,4,5,6,7",
958 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
963 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
964 "Counter": "0,1,2,3,4,5,6,7",
965 "CounterMask": "4",
968 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
973 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
974 "Counter": "0,1,2,3,4,5,6,7",
975 "CounterMask": "1",
978 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
983 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
984 "Counter": "0,1,2,3,4,5,6,7",
988 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
993 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
994 "Counter": "0,1,2,3,4,5,6,7",
998 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1003 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1004 "Counter": "0,1,2,3,4,5,6,7",
1005 "CounterMask": "4",
1008 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1013 …"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread…
1014 "Counter": "0,1,2,3,4,5,6,7",
1015 "CounterMask": "1",
1018 "Invert": "1",
1024 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1025 "Counter": "0,1,2,3,4,5,6,7",
1032 "BriefDescription": "Counts the number of x87 uops dispatched.",
1033 "Counter": "0,1,2,3,4,5,6,7",
1036 "PublicDescription": "Counts the number of x87 uops executed.",
1042 "Counter": "0,1,2,3,4,5,6,7",
1045 …"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to…
1051 "Counter": "0,1,2,3,4,5,6,7",
1052 "CounterMask": "1",
1060 "Counter": "0,1,2,3,4,5,6,7",
1061 "CounterMask": "1",
1069 "BriefDescription": "Retired uops except the last uop of each instruction.",
1070 "Counter": "0,1,2,3,4,5,6,7",
1073 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1079 "Counter": "0,1,2,3,4,5,6,7",
1088 …of the Topdown Slots event that are utilized by operations that eventually get retired (committed)…
1089 "Counter": "0,1,2,3,4,5,6,7",
1092 …of the Topdown Slots event that are utilized by operations that eventually get retired (committed)…
1098 "Counter": "0,1,2,3,4,5,6,7",
1099 "CounterMask": "1",
1102 "Invert": "1",