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/linux-6.12.1/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl502d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_WAIT_FOR_IDLE 0x0110
30 …_WAIT_FOR_IDLE_V 31:0
32 …_SET_DST_CONTEXT_DMA 0x0184
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
35 …_SET_SRC_CONTEXT_DMA 0x0188
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
38 …_SET_SEMAPHORE_CONTEXT_DMA 0x018c
[all …]
Dcl902d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_WAIT_FOR_IDLE 0x0110
31 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_FORMAT 0x0200
34 …_SET_DST_FORMAT_V 7:0
35 …_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
36 …_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
37 …_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
[all …]
Dcl5039.h2 * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
[all …]
/linux-6.12.1/arch/powerpc/lib/
Dfeature-fixups-test.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <asm/feature-fixups.h>
9 #include <asm/asm-compat.h>
10 #include <asm/ppc-opcode.h>
48 or 31,31,31
52 or 31,31,31
68 or 31,31,31
69 or 31,31,31
83 or 31,31,31
84 or 31,31,31
[all …]
/linux-6.12.1/arch/powerpc/xmon/
Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
135 #define UNUSED 0
136 { 0, 0, NULL, NULL, 0 },
142 #define BI_MASK (0x1f << 16)
143 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
148 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
152 #define BB_MASK (0x1f << 11)
[all …]
/linux-6.12.1/tools/arch/x86/kcpuid/
Dcpuid.csv1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v1.0
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
12 # Leaf 0H
15 … 0, 0, eax, 31:0, max_std_leaf , Highest cpuid standard leaf supported
16 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
23 1, 0, eax, 3:0, stepping , Stepping ID
[all …]
/linux-6.12.1/drivers/net/dsa/sja1105/
Dsja1105_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
90 /* MAC-Level Diagnostic Counters */
94 .offset = 0,
95 .start = 31,
101 .offset = 0x0,
108 .offset = 0x0,
115 .offset = 0x0,
117 .end = 0,
119 /* MAC-Level Diagnostic Flags */
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_ste_v2.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
7 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_0 = 0x00,
8 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1 = 0x01,
9 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_2 = 0x02,
10 DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_0 = 0x08,
11 DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_1 = 0x09,
12 DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0 = 0x0e,
13 DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0 = 0x18,
14 DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_1 = 0x19,
15 DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_0 = 0x40,
[all …]
/linux-6.12.1/Documentation/userspace-api/media/v4l/
Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/
Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
23 MT_HIF0 = 0x0,
25 MT_LMAC_AC00 = 0x0,
29 MT_LMAC_ALTX0 = 0x10,
36 MT_TXS_MPDU_FMT = 0,
40 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
42 #define MT_TX_FREE_COUNT GENMASK(12, 0)
43 /* 0: success, others: dropped */
46 #define MT_TX_FREE_PAIR BIT(31)
48 #define MT_TX_FREE_RATE GENMASK(13, 0)
[all …]
Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
9 MT_HIF0 = 0x0,
11 MT_LMAC_AC00 = 0x0,
15 MT_LMAC_ALTX0 = 0x10,
24 #define MT_RXD0_LENGTH GENMASK(15, 0)
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
32 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
33 #define MT_RXD0_SW_PKT_TYPE_MAP 0x380F
34 #define MT_RXD0_SW_PKT_TYPE_FRAME 0x3801
37 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0)
[all …]
/linux-6.12.1/drivers/video/fbdev/nvidia/
Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
[all …]
/linux-6.12.1/arch/powerpc/crypto/
Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
16 # clamp r &= 0x0FFFFFFC0FFFFFFC 0x0FFFFFFC0FFFFFFF
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
[all …]
/linux-6.12.1/arch/mips/include/asm/octeon/
Dcvmx-ciu2-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 …ine CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * …
32 …ine CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * …
33 … CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * …
34 …CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * …
35 …CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * …
36 …_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * …
37 …_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * …
[all …]
/linux-6.12.1/drivers/net/ipa/reg/
Dipa_reg-v3.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [COMP_CFG_ENABLE] = BIT(0),
18 /* Bits 5-31 reserved */
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
24 [CLKON_RX] = BIT(0),
41 /* Bits 17-31 reserved */
44 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
47 [ROUTE_DIS] = BIT(0),
52 /* Bits 22-23 reserved */
[all …]
Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
13 [MAX_PIPES] = GENMASK(7, 0),
16 [PROD_LOWEST] = GENMASK(31, 24),
19 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
39 /* Bits 17-18 reserved */
44 /* Bits 28-29 reserved */
46 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
49 REG_FIELDS(COMP_CFG, comp_cfg, 0x00000048);
[all …]
Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
13 [MAX_PIPES] = GENMASK(7, 0),
16 [PROD_LOWEST] = GENMASK(31, 24),
19 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
45 /* Bits 28-29 reserved */
47 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
50 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
53 [CLKON_RX] = BIT(0),
[all …]
Dipa_reg-v3.5.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [COMP_CFG_ENABLE] = BIT(0),
18 /* Bits 5-31 reserved */
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
24 [CLKON_RX] = BIT(0),
46 /* Bits 22-31 reserved */
49 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
52 [ROUTE_DIS] = BIT(0),
57 /* Bits 22-23 reserved */
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtw89/
Dcam.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
12 #define RTW89_BSSID_MATCH_ALL GENMASK(5, 0)
13 #define RTW89_BSSID_MATCH_5_BYTES GENMASK(4, 0)
17 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0)); in FWCMD_SET_ADDR_IDX()
32 le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(0)); in FWCMD_SET_ADDR_VALID()
72 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(31, 24)); in FWCMD_SET_ADDR_TMA_HASH()
77 le32p_replace_bits((__le32 *)(cmd) + 3, value, GENMASK(5, 0)); in FWCMD_SET_ADDR_BSSID_CAM_IDX()
82 le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(7, 0)); in FWCMD_SET_ADDR_SMA0()
97 le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(31, 24)); in FWCMD_SET_ADDR_SMA3()
[all …]
Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
13 #define DATA_RATE_MODE_NON_HT 0x0
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
16 #define DATA_RATE_MODE_HT 0x1
19 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)
21 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
22 #define DATA_RATE_MODE_VHT 0x2
23 #define DATA_RATE_MODE_HE 0x3
[all …]
/linux-6.12.1/drivers/ras/amd/atl/
Dreg_fields.h1 /* SPDX-License-Identifier: GPL-2.0 */
50 * D18F1x208 [System Fabric ID Mask 0]
51 * DF3 ComponentIdMask [9:0]
53 * D18F1x150 [System Fabric ID Mask 0]
54 * DF3p5 ComponentIdMask [15:0]
56 * D18F4x1B0 [System Fabric ID Mask 0]
57 * DF4 ComponentIdMask [15:0]
58 * DF4p5 ComponentIdMask [15:0]
60 #define DF3_COMPONENT_ID_MASK GENMASK(9, 0)
61 #define DF4_COMPONENT_ID_MASK GENMASK(15, 0)
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
24 #define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
39 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
[all …]
/linux-6.12.1/arch/arc/include/asm/
Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
23 * This is a pure count, so (1-32) or (0-31) doesn't apply
24 * It could be 0 to 32, based on num of 0's in there
25 * clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
32 " norm.f %0, %1 \n" in clz()
33 " mov.n %0, 0 \n" in clz()
34 " add.p %0, %0, 1 \n" in clz()
47 return 0; in constant_fls()
48 if (!(x & 0xffff0000u)) { in constant_fls()
[all …]
/linux-6.12.1/tools/testing/selftests/hid/tests/
Dtest_multitouch.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
20 KERNEL_MODULE = ("hid-multitouch", "hid_multitouch")
28 "NOT_SEEN_MEANS_UP": BIT(0),
66 self.azimuth = 0
74 super().__init__(0, x, y)
80 self.twist = 0
91 Usage Page (0xff00)
92 Usage (0xc5)
93 Logical Minimum (0)
[all …]
/linux-6.12.1/arch/alpha/include/asm/
Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
51 .prologue 0 \n\
55 ldq $0,0($17) \n\
56 ldq $1,0($18) \n\
73 xor $0,$1,$0 # 7 cycles from $1 load \n\
77 stq $0,0($17) \n\
106 .prologue 0 \n\
110 ldq $0,0($17) \n\
[all …]

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